公开(公告)号：US07502657B2

公开(公告)日：2009-03-10

申请号：US10206088

申请日：2002-07-29

申请人： Yohei Nakata ,  Keisuke Inoue ,  Junichiro Sakata

发明人： Yohei Nakata ,  Keisuke Inoue ,  Junichiro Sakata

IPC分类号： G06F17/00

CPC分类号： G10H1/0025 ,  G10H2220/101

摘要： An information processing apparatus/method allows a user to interactively combine a plurality of sound chips into music data, edit music data, and play it back, by inputting data or commands via a keyboard or a mouse. A chip such as a sound pattern, a one-shot patter, or an effect to be applied to a sound pattern or a one-shot pattern is assigned to each key of a keyboard. If a user presses a key, a chip corresponding to a pressed key is executed. When a plurality of keys are simultaneously pressed, corresponding chips are played in a superimposed fashion. A piece of music can be composed by sequentially pressing various keys thereby sequentially combining corresponding chips.

摘要翻译： 信息处理装置/方法允许用户通过经由键盘或鼠标输入数据或命令，将多个声音芯片交互地组合成音乐数据，编辑音乐数据，以及播放它们。 将诸如声音图案，单次图案或要应用于声音图案或单次图案的效果的芯片分配给键盘的每个键。 如果用户按下键，则执行与按下的键对应的芯片。 当同时按下多个按键时，以叠加的方式播放相应的芯片。 可以通过顺序地按各种按键来组合一段音乐，从而顺序地组合对应的码片。

公开(公告)号：US20130223137A1

公开(公告)日：2013-08-29

申请号：US13816718

申请日：2011-08-14

申请人： Masahiko Yoshimoto ,  Hiroshi Kawaguchi ,  Yohei Nakata ,  Shunsuke Okumura

发明人： Masahiko Yoshimoto ,  Hiroshi Kawaguchi ,  Yohei Nakata ,  Shunsuke Okumura

IPC分类号： G11C11/417

CPC分类号： G11C11/417 ,  G11C8/12 ,  G11C8/14 ,  G11C11/412 ,  G11C11/413 ,  G11C15/00 ,  G11C15/04 ,  G11C29/74 ,  G11C2211/5641

摘要： Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.

摘要翻译： 提供了能够动态地改变存储单元位可靠性和切换操作模式以适应过程变化的存储器，从而降低工作电压。 存储器设置有模式控制线选择电路，用于将模式控制线分成单位，并且使用控制线选择信号和全局控制信号来控制分成字单元的模式控制线，以及字线选择电路，用于将 控制开关单元导通到单元的字线，并使用字线选择信号和全局字信号来控制划分为字单位的字线。 模式控制线切换电路用于以单位单位在1位/ 1个单元模式和1位/ n单元模式之间切换。

公开(公告)号：US4075506A

公开(公告)日：1978-02-21

申请号：US662513

申请日：1976-03-01

申请人： Yohei Nakata

发明人： Yohei Nakata

IPC分类号： H01H43/12 ,  H01H43/00

CPC分类号： H01H43/121 ,  Y10T307/773 ,  Y10T307/951

摘要： A timing apparatus comprising a time plate equipped with light transmitting holes or brushes which are positioned, at points representative of times and arranged at equal intervals in at least one row. The light transmitting holes or brushes serve as logical connection elements indicating such times. At least two rotators are coaxially disposed inside the time plate in a rotatable manner and also have light transmitting holes or brushes respectively corresponding with the logical connection elements on the time plate. The relative speeds of rotation of the time plate and the rotators are predetermined in such a manner so that the position of each logical connection element on the time plate and the positions of the corresponding logical connection elements on the rotators come into alignment at a given time indicated by the elements, thereby effecting electrical or optical timing connection at a desired time.

公开(公告)号：US08787075B2

公开(公告)日：2014-07-22

申请号：US13816718

申请日：2011-08-14

申请人： Masahiko Yoshimoto ,  Hiroshi Kawaguchi ,  Yohei Nakata ,  Shunsuke Okumura

发明人： Masahiko Yoshimoto ,  Hiroshi Kawaguchi ,  Yohei Nakata ,  Shunsuke Okumura

IPC分类号： G11C11/00 ,  G11C11/412 ,  G11C11/417 ,  G11C8/12 ,  G11C15/04 ,  G11C11/413 ,  G11C8/14 ,  G11C15/00

CPC分类号： G11C11/417 ,  G11C8/12 ,  G11C8/14 ,  G11C11/412 ,  G11C11/413 ,  G11C15/00 ,  G11C15/04 ,  G11C29/74 ,  G11C2211/5641

摘要： Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.

摘要翻译： 提供了能够动态地改变存储单元位可靠性和切换操作模式以适应过程变化的存储器，从而降低工作电压。 存储器设置有模式控制线选择电路，用于将模式控制线分成单位，并且使用控制线选择信号和全局控制信号来控制分成字单元的模式控制线，以及字线选择电路，用于将 控制开关单元导通到单元的字线，并使用字线选择信号和全局字信号来控制划分为字单位的字线。 模式控制线切换电路用于以单位单位在1位/ 1个单元模式和1位/ n单元模式之间切换。