公开(公告)号：US06603175B2

公开(公告)日：2003-08-05

申请号：US09855693

申请日：2001-05-16

申请人： Tadao Kadowaki ,  Akihiko Ebina ,  Masayuki Yamaguchi ,  Yoko Sato

发明人： Tadao Kadowaki ,  Akihiko Ebina ,  Masayuki Yamaguchi ,  Yoko Sato

IPC分类号： H01L2701

CPC分类号： G04G19/06 ,  H01L27/1203 ,  H01L29/7841 ,  H01L2924/0002 ,  H03K19/00384 ,  H01L2924/00

摘要： A semiconductor integrated circuit comprising: a first power line which supplies a first voltage potential; a second power line which supplies a second voltage potential that is lower than the first voltage potential; a voltage regulator circuit connected electrically to the first and second power lines; a third power line which supplies a constant voltage generated by a voltage regulator circuit, with reference to the first voltage potential; and an operating circuit connected electrically to the first and third power lines. At least one transistor configuring the voltage regulator circuit is a partially-depleted SOI field-effect transistor in which a body region and a source region are connected electrically. At least one transistor configuring the operating circuit is a partially-depleted SOI field-effect transistor in which a body region is in an electrically floating state.

摘要翻译： 一种半导体集成电路，包括：提供第一电压电位的第一电力线; 第二电源线，其提供低于所述第一电压电位的第二电压电位; 电压调节器电路，其电连接到所述第一和第二电力线; 第三电源线，其相对于所述第一电压电位提供由电压调节器电路产生的恒定电压; 以及与第一和第三电力线电连接的操作电路。 配置电压调节器电路的至少一个晶体管是部分耗尽的SOI场效应晶体管，其中主体区域和源极区域电连接。 构成操作电路的至少一个晶体管是其中体区处于电浮动状态的部分耗尽的SOI场效应晶体管。

公开(公告)号：US06709908B2

公开(公告)日：2004-03-23

申请号：US09791984

申请日：2001-02-23

申请人： Yoko Sato ,  Akihiko Ebina

发明人： Yoko Sato ,  Akihiko Ebina

IPC分类号： H01L2184

CPC分类号： H01L21/76264 ,  H01L21/76281 ,  H01L27/1203

摘要： Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

摘要翻译： 某些实施例涉及制造抑制寄生器件形成的半导体器件的方法。 制造半导体器件的方法包括限定步骤和掺杂剂注入步骤。 定界步骤部分氧化设置在半导体衬底11上的单晶硅层，其间具有绝缘层，以形成由绝缘层16限定的多个隔离的单晶硅层段13a。在注入步骤中，掺杂剂 将离子18注入到单晶硅层段13a中以激活单晶硅层段13a。 在该注入步骤中，通过注入能量将掺杂剂注入到单晶硅层段13a中，所述注入能量被设定为使得掺杂剂浓度的最大值的位置位于每个单晶的底部边缘Ea和Eb 硅层段13a。

公开(公告)号：US07592684B2

公开(公告)日：2009-09-22

申请号：US11461165

申请日：2006-07-31

申请人： Takafumi Noda ,  Masahiro Hayashi ,  Akihiko Ebina ,  Masahiko Tsuyuki

发明人： Takafumi Noda ,  Masahiro Hayashi ,  Akihiko Ebina ,  Masahiko Tsuyuki

IPC分类号： H01L27/12

CPC分类号： H01L21/823418 ,  H01L21/823462

摘要： A semiconductor device is provided in which high breakdown voltage transistors and low voltage driving transistors are formed on the same substrate. The device includes a semiconductor layer, first element isolation regions for defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions including trench dielectric layers for defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating the electric field of the high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, wherein upper ends of the offset dielectric layers are beak shaped.

摘要翻译： 提供了一种半导体器件，其中在相同的衬底上形成有高的击穿电压晶体管和低电压驱动晶体管。 所述器件包括半导体层，用于限定半导体层中的高击穿电压晶体管形成区域的第一元件隔离区域，包括用于限定半导体层中的低电压驱动晶体管形成区域的沟槽电介质层的第二元件隔离区域，高击穿电压 形成在高击穿电压晶体管形成区域中的晶体管，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻形成在高击穿电压晶体管形成区域中的高击穿电压晶体管的电场的偏移电介质层， 其中偏移电介质层的上端为喙状。

公开(公告)号：US07005328B2

公开(公告)日：2006-02-28

申请号：US10939330

申请日：2004-09-14

申请人： Akihiko Ebina ,  Susumu Inoue

发明人： Akihiko Ebina ,  Susumu Inoue

IPC分类号： H01L21/82

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

摘要翻译： 具有存储单元的半导体器件。 每个存储单元具有形成在半导体衬底上的字栅，其中插入有第一栅极绝缘层，杂质层以及具有侧壁形状的第一和第二控制栅极。 将杂质层相互相邻的第一和第二控制栅极连接到公共接触部分。 公共接触部分包括第一接触导电层，第二接触导电层和焊盘形第三接触导电层。 第三接触导电层形成在第一和第二接触导电层上。

公开(公告)号：US20050045983A1

公开(公告)日：2005-03-03

申请号：US10899298

申请日：2004-07-26

申请人： Takafumi Noda ,  Masahiro Hayashi ,  Akihiko Ebina ,  Masahiko Tsuyuki

发明人： Takafumi Noda ,  Masahiro Hayashi ,  Akihiko Ebina ,  Masahiko Tsuyuki

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/00

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

摘要： A semiconductor device is provided that includes a semiconductor layer, first element isolation regions defining a high breakdown voltage transistor forming region in the semiconductor layer, second element isolation regions defining a low voltage driving transistor forming region in the semiconductor layer, high breakdown voltage transistors formed in the high breakdown voltage transistor forming region, low voltage driving transistors formed in the low voltage driving transistor forming region, and offset dielectric layers for alleviating an electric field of the high breakdown voltage transistors, wherein the high breakdown voltage transistors have gate dielectric layers formed by a CVD method.

摘要翻译： 提供一种半导体器件，其包括半导体层，在半导体层中限定高击穿电压晶体管形成区域的第一元件隔离区域，限定半导体层中的低电压驱动晶体管形成区域的第二元件隔离区域，形成的高击穿电压晶体管 在高击穿电压晶体管形成区域中，形成在低电压驱动晶体管形成区域中的低电压驱动晶体管，以及用于减轻高击穿电压晶体管的电场的偏移电介质层，其中高击穿电压晶体管形成栅极电介质层 通过CVD法。

公开(公告)号：US06504213B1

公开(公告)日：2003-01-07

申请号：US09626606

申请日：2000-07-27

申请人： Akihiko Ebina

发明人： Akihiko Ebina

IPC分类号： H01L2701

CPC分类号： H01L29/66772 ,  H01L29/4908 ,  H01L29/78615

摘要： A dynamic threshold-voltage MOSFET (DTMOS) enables a low power consumption, even during use under conditions of a comparatively high gate voltage. A first contact portion and a gate electrode are placed in electrical contact by a resistance portion. A part of an interconnecting portion is utilized as the resistance portion, by making the width of the part of the interconnecting portion smaller than the width of a remaining part of the interconnecting portion. The forward-direction current flowing through a PN junction formed by a body region and a source region is limited by the resistance portion, even when a comparatively high voltage is applied to the gate electrode. Thus the current between the body region and the source region can be held low. As a result, the power consumption can be reduced, even when the MOS field-effect transistor is used under conditions of a comparatively high gate voltage.

摘要翻译： 即使在栅极电压相对较高的条件下使用时，动态阈值电压MOSFET（DTMOS）也能实现低功耗。 第一接触部分和栅电极通过电阻部分电接触。 通过使互连部分的宽度小于互连部分的剩余部分的宽度，将互连部分的一部分用作电阻部分。 即使向栅电极施加比较高的电压，流过由体区域和源极区域形成的PN结的正向电流被电阻部分限制。 因此，可以将身体区域和源区域之间的电流保持为低。 结果，即使在栅极电压相对较高的条件下使用MOS场效应晶体管，也可以降低功耗。

公开(公告)号：US20050148138A1

公开(公告)日：2005-07-07

申请号：US10961767

申请日：2004-10-07

申请人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

发明人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

IPC分类号： H01L21/283 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/115

摘要： A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation. The method also includes a step of removing the stack film formed in the low-voltage driving transistor forming region, a step of forming a second gate insulating layer in the low-voltage driving transistor forming region, a step of forming gate electrodes in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region and a step of forming source/drain regions in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region.

摘要翻译： 制造具有高击穿电压晶体管，低电压驱动晶体管和MONOS型存储晶体管的半导体器件的方法包括形成至少包含氧化硅层和氮化硅层的堆叠膜的步骤 通过形成高击穿电压晶体管的高击穿电压晶体管形成区域，形成低电压驱动晶体管的低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域 存储晶体管形成在半导体层中，去除形成在高击穿电压晶体管的第一栅极绝缘层形成区域中的堆叠膜的步骤和形成高击穿电压的第一栅极绝缘层的步骤 晶体管形成区域通过热氧化。 该方法还包括去除在低电压驱动晶体管形成区域中形成的叠层膜的步骤，在低电压驱动晶体管形成区域中形成第二栅极绝缘层的步骤，在高电压驱动晶体管形成区域中形成栅电极的步骤 低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域，以及在高击穿电压晶体管形成区域中形成源极/漏极区域的步骤，低电压驱动晶体管形成区域 形成区域和MONOS型存储晶体管形成区域。

公开(公告)号：US06762465B2

公开(公告)日：2004-07-13

申请号：US10050793

申请日：2002-01-18

申请人： Akihiko Ebina

发明人： Akihiko Ebina

IPC分类号： H01L2970

CPC分类号： H01L27/1203 ,  H01L29/7317

摘要： A semiconductor device 1000 may include first and second switch elements 1000A and 1000B formed in first and second element forming regions 16a and 16b of a SOI layer 10a, respectively. The first and second switch elements 1000A and 1000B form a BiCMOS inverter circuit, and each includes a field effect transistor and a bi-polar transistor. A first p-type body region 50a is electrically connected to an n-type source region 120. The first p-type body region 50a is electrically connected to a first p-type base region 220. A second n-type body region 54a is electrically connected to a second n-type collector region 430. A p-type drain region 330 is electrically connected to a second p-type base region 420.

摘要翻译： 半导体器件1000可以包括分别形成在SOI层10a的第一和第二元件形成区域16a和16b中的第一和第二开关元件1000A和100​​0B。 第一和第二开关元件1000A和100​​0B形成BiCMOS反相器电路，并且每个包括场效应晶体管和双极晶体管。 第一p型体区域50a电连接到n型源极区域120.第一p型体区域50a电连接到第一p型基极区域220.第二n型体区域54a是 电连接到第二n型集电极区域430.p型漏极区域330电连接到第二p型基极区域420。

公开(公告)号：US06521948B2

公开(公告)日：2003-02-18

申请号：US09731922

申请日：2000-12-08

申请人： Akihiko Ebina

发明人： Akihiko Ebina

IPC分类号： H01L2701

CPC分类号： H01L29/4908 ,  H01L29/42384 ,  H01L29/78609

摘要： A SOI-structure MOS field-effect transistor. In this transistor, a gate electrode and a p− region that is a body region are placed into electrical contact by a PN junction portion. An n+-type portion of the PN junction portion is in electrical contact with the gate electrode and a p+-type portion of the PN junction portion is in electrical contact with a p− region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.

摘要翻译： SOI结构MOS场效应晶体管。 在该晶体管中，作为体区的栅电极和p区被PN结部分电接触。 PN结部分的n +型部分与栅电极电接触，并且PN结部分的p +型部分与p-区电接触。 当向栅电极施加正电压时，上述配置确保了向PN结部分施加反向电压，使得仅PN电阻的反向泄漏电流的小电流沿着从 栅电极，PN结部分和体区，并进入源区。

公开(公告)号：US5304925A

公开(公告)日：1994-04-19

申请号：US798141

申请日：1991-11-26

申请人： Akihiko Ebina

发明人： Akihiko Ebina

IPC分类号： H01L21/66 ,  G01R31/27 ,  G01R31/26

CPC分类号： G01R31/27

摘要： A test circuit for evaluating the characteristics of an component formed on the surface of a semi-conductor substrate. The test circuit comprises at least two MOS field effect transistors having the same gate width and different gate lengths, and measuring electrodes mounted on opposite ends of each gate and enageable with probes when measuring the test circuit. The test circuit measures typical characteristic data of MOSFETs to be used in a semiconductor device with good match by an electrical means.

摘要翻译： 一种用于评估形成在半导体基板的表面上的部件的特性的测试电路。 测试电路包括具有相同栅极宽度和不同栅极长度的至少两个MOS场效应晶体管，以及安装在每个栅极的相对端上的测量电极，并且在测量测试电路时可与探头配合使用。 测试电路测量要用于通过电气装置良好匹配的半导体器件中的MOSFET的典型特征数据。