公开(公告)号：US20080081432A1

公开(公告)日：2008-04-03

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07709346B2

公开(公告)日：2010-05-04

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20050001252A1

公开(公告)日：2005-01-06

申请号：US10858727

申请日：2004-06-02

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07183600B2

公开(公告)日：2007-02-27

申请号：US10858727

申请日：2004-06-02

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20050014338A1

公开(公告)日：2005-01-20

申请号：US10649262

申请日：2003-08-26

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

公开(公告)号：US20050275014A1

公开(公告)日：2005-12-15

申请号：US11195525

申请日：2005-08-01

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

公开(公告)号：US06939765B2

公开(公告)日：2005-09-06

申请号：US10649262

申请日：2003-08-26

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

摘要翻译： 本发明的实施例涉及集成电路器件和用于形成器件的方法。 在本发明的一些实施例中，在单个衬底上形成两种类型的晶体管，晶体管：具有凹陷栅极的晶体管，以及具有平面栅电极的晶体管。 在其他实施例中，具有凹陷栅极的晶体管形成在相同衬底的多个区域中。 此外，可以同时形成多于一个区域中的晶体管的栅极。

公开(公告)号：US06696722B1

公开(公告)日：2004-02-24

申请号：US09708957

申请日：2000-11-08

申请人： Hyoung-Sub Kim

发明人： Hyoung-Sub Kim

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L21/32137 ,  H01L21/76895 ,  H01L28/60

摘要： A storage node of a DRAM cell capacitor includes a first insulating layer in which a bit line pattern is formed, a second insulating layer formed on the first insulating layer of which material is different from that of the second insulating layer, a first conductive layer formed on the second insulating layer that has an etching rate different from that of the first conductive layer, a material layer formed on the first conductive layer, which has a smaller width than the first conductive layer and is made of material with different etching characteristics from that of the first conductive layer, a second conductive layer that is formed on the material layer and has the same width as that of the material layer, and a sidewall conductive spacer that is an contact with the second conductive layer and the material layer and is formed on the top surface of the first conductive layer and on sides of the material layer and the second conductive layer.

摘要翻译： DRAM单元电容器的存储节点包括其中形成位线图形的第一绝缘层，形成在与第二绝缘层的材料不同的第一绝缘层上的第二绝缘层，形成的第一导电层 在具有与第一导电层不同的蚀刻速率的第二绝缘层上，形成在第一导电层上的材料层，其宽度小于第一导电层，并且由与第一导电层不同的蚀刻特性的材料制成 形成在所述材料层上并且具有与所述材料层的宽度相同的宽度的第二导电层，以及与所述第二导电层和所述材料层接触形成的侧壁导电间隔物， 在第一导电层的顶表面上以及材料层和第二导电层的侧面上。

公开(公告)号：US11439222B2

公开(公告)日：2022-09-13

申请号：US17041048

申请日：2020-07-15

申请人： Hyoung-Sub Kim

发明人： Hyoung-Sub Kim

IPC分类号： A45D44/10 ,  A45D19/00 ,  A45D19/10 ,  A47K3/12

摘要： The proposed is directed to a shampoo assisting device that is mounted on a wash basin, a bathtub, a sink, etc. with a simple configuration to allow the user to be shampooed while lying down. The shampoo assisting device includes a main body having a locking part provided on one side and a headrest part provided on the other side to support a user's head, and a first support protruding from a lower portion of the main body so as to be closely supported by a bottom surface of a wash basin.

公开(公告)号：US07592215B2

公开(公告)日：2009-09-22

申请号：US11463814

申请日：2006-08-10

申请人： Hyoung-Sub Kim

发明人： Hyoung-Sub Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/76831 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894

摘要： According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.

摘要翻译： 根据本发明的实施例，字线图形被放置在单元阵列区域中的半导体衬底上，并且至少一个栅极图案被放置在外围电路区域中的半导体衬底上。 字线图案和栅极图案的侧壁分别用与字线间隔件宽度相同的字线间隔物和栅极间隔物覆盖。 具有字线间隔物和栅极间隔物的半导体衬底被层间绝缘层覆盖。 形成在层间绝缘层中的自对准接触孔穿过字线图案之间的预定区域。 通过蚀刻层间绝缘层和字线间隔物形成自对准接触孔。 自对准接触孔的侧壁被具有与栅极间隔物的宽度不同的宽度的自对准接触间隔物覆盖。