公开(公告)号：US20080081432A1

公开(公告)日：2008-04-03

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07709346B2

公开(公告)日：2010-05-04

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07183600B2

公开(公告)日：2007-02-27

申请号：US10858727

申请日：2004-06-02

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20050001252A1

公开(公告)日：2005-01-06

申请号：US10858727

申请日：2004-06-02

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20050014338A1

公开(公告)日：2005-01-20

申请号：US10649262

申请日：2003-08-26

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

公开(公告)号：US20050275014A1

公开(公告)日：2005-12-15

申请号：US11195525

申请日：2005-08-01

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

公开(公告)号：US06939765B2

公开(公告)日：2005-09-06

申请号：US10649262

申请日：2003-08-26

申请人： Ji-Young Kim ,  Hyoung-Sub Kim

发明人： Ji-Young Kim ,  Hyoung-Sub Kim

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L21/823456 ,  H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897

摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

摘要翻译： 本发明的实施例涉及集成电路器件和用于形成器件的方法。 在本发明的一些实施例中，在单个衬底上形成两种类型的晶体管，晶体管：具有凹陷栅极的晶体管，以及具有平面栅电极的晶体管。 在其他实施例中，具有凹陷栅极的晶体管形成在相同衬底的多个区域中。 此外，可以同时形成多于一个区域中的晶体管的栅极。

公开(公告)号：US10296114B2

公开(公告)日：2019-05-21

申请号：US12788669

申请日：2010-05-27

申请人： Moon-Jae Lee ,  Won-Jun Song ,  Sun-Hee Lee ,  Young-Hee Lee ,  Mu-Hyun Kim ,  Hye-Dong Kim ,  Ji-Young Kim

发明人： Moon-Jae Lee ,  Won-Jun Song ,  Sun-Hee Lee ,  Young-Hee Lee ,  Mu-Hyun Kim ,  Hye-Dong Kim ,  Ji-Young Kim

IPC分类号： G06F3/041 ,  G06F3/042 ,  H01L27/12

摘要： A touch screen display apparatus including a sensor unit to sense and to process light signals and a pixel unit to drive pixels according to the light signal processing performed by the sensor unit. The touch screen display apparatus includes a substrate; a plurality of pixel units disposed on the substrate, wherein each of the pixel units includes a first electrode, a second electrode, and an emission layer interposed between the first electrode and the second electrode; and a plurality of sensor units disposed on the substrate, wherein each of the sensor units includes a sensor first electrode, a sensor second electrode, and an organic light receiving layer interposed between the sensor first electrode and the sensor second electrode.

公开(公告)号：US09330960B2

公开(公告)日：2016-05-03

申请号：US14296850

申请日：2014-06-05

申请人： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

发明人： Young-Seung Cho ,  Sung-Eui Kim ,  Ji-Young Kim ,  Hoon Jeong ,  Chan-Won Kim ,  Jong-Bom Seo ,  Seung-Jun Lee ,  Jun-Soo Lee

IPC分类号： H01L21/00 ,  H01L21/764 ,  H01L49/02 ,  H01L27/108

CPC分类号： H01L28/88 ,  H01L21/764 ,  H01L27/10808 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/90

摘要： A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.

摘要翻译： 半导体器件包括第一电容器结构，第二电容器结构和绝缘图案。 第一电容器结构包括顺序堆叠在基板上的第一下电极，第一电介质层和第一上电极。 第二电容器结构包括第二下电极，第二电介质层和顺序堆叠在基板上并与第一电容器结构相邻的第二上电极。 绝缘图案部分地填充第一和第二电容器结构之间的空间，并且在绝缘图案上的第一和第二电容器结构之间形成气隙。

公开(公告)号：US09035330B2

公开(公告)日：2015-05-19

申请号：US13088261

申请日：2011-04-15

申请人： Jin-Goo Kang ,  Mu-Hyun Kim ,  Jae-Bok Kim ,  Dong-Kyu Lee ,  Ji-Young Kim

发明人： Jin-Goo Kang ,  Mu-Hyun Kim ,  Jae-Bok Kim ,  Dong-Kyu Lee ,  Ji-Young Kim

IPC分类号： H01L33/00 ,  H01L29/04 ,  H01L31/036 ,  H01L27/32 ,  H01L51/52

CPC分类号： H01L27/3246 ,  H01L51/5237 ,  H01L51/524 ,  H01L51/5253

摘要： An organic light-emitting display device and a method of manufacturing the same are disclosed. The organic light-emitting display device includes: a substrate, a plurality of pixels on the substrate, a plurality of first electrodes, each disposed in each of the plurality of pixels, a pixel defining layer including a first pixel defining sub-layer disposed between each two adjacent first electrodes, and a second pixel defining sub-layer covering the first pixel defining sub-layer and surface edge portions of each two adjacent first electrodes, an intermediate layer disposed on each of the first electrodes and including an emission layer, and a second electrode configured to face the first electrodes.

摘要翻译： 公开了一种有机发光显示装置及其制造方法。 有机发光显示装置包括：基板，基板上的多个像素，多个第一电极，每个设置在多个像素中的每一个中;像素限定层，包括限定子层的第一像素， 每个两个相邻的第一电极，以及限定子层的第二像素，覆盖限定每个两个相邻的第一电极的子层和表面边缘部分的第一像素，设置在每个第一电极上并包括发射层的中间层，以及 配置成面对第一电极的第二电极。