摘要:
Disclosed herein is a thin film deposition apparatus having a reaction chamber for forming a thin film on a plurality of substrates rested on a susceptor. The apparatus comprises: a gas supply means for supplying a plurality of gases to the inside of the reaction chamber from the outside, the gases including a reaction gas; a gas distribution means for distributing and spraying the gases supplied from the gas supply means so as to conform to the purpose of a process; a gas retaining means having a plurality of reaction cells for partitionally accommodating and retaining the respective gases distributed from the gas distribution means; a rotation driving means for rotating the gas retaining means such that the gases retained in the respective reaction cells are exposed to the substrates in sequence; and a gas exhaust means for pumping the gases retained by the gas retaining means to the outside of the reaction chamber.
摘要:
Disclosed herein is a thin film deposition apparatus having a reaction chamber for forming a thin film on a plurality of substrates rested on a susceptor. The apparatus comprises: a gas supply means for supplying a plurality of gases to the inside of the reaction chamber from the outside, the gases including a reaction gas; a gas distribution means for distributing and spraying the gases supplied from the gas supply means so as to conform to the purpose of a process; a gas retaining means having a plurality of reaction cells for partitionally accommodating and retaining the respective gases distributed from the gas distribution means; a rotation driving means for rotating the gas retaining means such that the gases retained in the respective reaction cells are exposed to the substrates in sequence; and a gas exhaust means for pumping the gases retained by the gas retaining means to the outside of the reaction chamber.
摘要:
A semiconductor memory device including an active matrix comprising a semiconductor substrate, a transistor formed on the semiconductor substrate and isolation regions for isolating the transistor, a first metal pattern formed on top of the active matrix and extending outside the transistor, a capacitor structure formed over the transistor, a barrier layer formed on top of the capacitor structure to improve thermal stability, and a second metal pattern formed on top of the capacitor structure to electrically connect the capacitor structure to the transistor through the first and second metal patterns.
摘要:
A method for fabricating a ferroelectric random access memory device, includes the steps of: forming an interlayer insulating layer on a ferroelectric capacitor and a transistor; forming a first opening through the interlayer insulating layer in order to expose a top electrode of the ferroelectric capacitor; forming the barrier metal layer on the resulting structure on which the first opening is formed, wherein the barrier metal layer is in contact with the top electrode of the ferroelectric capacitor; selectively etching the barrier metal and interlayer insulating layers and forming a second opening in order to expose a junction layer of the transistor; forming a polysilicon layer on the resulting structure and doping impurity ions into the polysilicon layer, wherein the doped polysilicon layer is in contact with the junction layer of the transistor; and selectively etching the polysilicon and barrier metal layers, thereby patterning an interconnection layer for interconnecting the transistor and the ferroelectric capacitor, wherein the capacitor is electrically in contact with the interconnection layer via the barrier metal layer and the transistor is electrically in contact with the interconnection layer.
摘要:
A semiconductor memory device includes an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate and isolation regions for isolating the transistor, a first metal line formed on top of the active matrix and extending outside the transistor, a capacitor structure formed over the transistor and a second metal line formed on top of the capacitor structure to electrically connect the capacitor structure to the transistor through the first and the second metal lines. In the memory device, forming the capacitor structure at the position over the transistor can reduce the cell size of the memory cell.