公开(公告)号：US09070424B2

公开(公告)日：2015-06-30

申请号：US13538869

申请日：2012-06-29

申请人： YongSik Youn ,  Sooho Cha ,  Chan-kyung Kim

发明人： YongSik Youn ,  Sooho Cha ,  Chan-kyung Kim

IPC分类号： G11C11/00 ,  G11C7/06 ,  G11C13/00 ,  G11C11/16

CPC分类号： G11C7/065 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0042

摘要： Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

摘要翻译： 示例性实施例包括电阻型存储读出放大器电路，其包括差分输出端，第一和第二输入端，预充电部分和其他组件，其被布置为使得电流在至少“设置”或“放大”阶段期间重新使用 ，从而降低电路的总体电流消耗，并提高抗噪声能力。 响应于参考线电流和位线电流之间的增量平均电流，使高阻抗输出端子的电压电平摆动。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。 还公开了电流镜电路，其可以与所公开的读出放大器电路结合使用。 在另一个实施例中，读出放大器电路包括读/写 - 写操作的能力。

公开(公告)号：US08885386B2

公开(公告)日：2014-11-11

申请号：US13659882

申请日：2012-10-24

申请人： YongSik Youn ,  Sooho Cha ,  DongSeok Kang ,  Chan-kyung Kim

发明人： YongSik Youn ,  Sooho Cha ,  DongSeok Kang ,  Chan-kyung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1084 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： Example embodiments include a level shifting write driver in a sense amplifier for a resistive type memory. The write driver may include a cross-coupled latch circuit, a first output section, a second output section, and an input section. The first output section includes one or more first driving transistors to drive a first current through the first output section and not through the cross-coupled latch. The second output section includes one or more second driving transistors configured to drive a second current through the second output section and not through the cross-coupled latch. The current flows of the outputs sections are isolated from the latch circuit. In some embodiments, no two PMOS type transistors are serially connected, thereby reducing the consumption of die area. In some embodiments, a single control signal is used to operate the write driver.

摘要翻译： 示例性实施例包括用于电阻型存储器的读出放大器中的电平移位写入驱动器。 写驱动器可以包括交叉耦合锁存电路，第一输出部分，第二输出部分和输入部分。 第一输出部分包括一个或多个第一驱动晶体管，以驱动通过第一输出部分的第一电流，而不是通过交叉耦合的锁存器。 第二输出部分包括一个或多个第二驱动晶体管，其构造成驱动第二电流通过第二输出部分而不通过交叉耦合的锁存器。 输出部分的电流流动与锁存电路隔离。 在一些实施例中，没有两个PMOS型晶体管串联连接，从而减少了管芯面积的消耗。 在一些实施例中，使用单个控制信号来操作写入驱动器。

公开(公告)号：US08750018B2

公开(公告)日：2014-06-10

申请号：US13488432

申请日：2012-06-04

申请人： YongSik Youn ,  Adrian Ong ,  Sooho Cha ,  Chan-kyung Kim

发明人： YongSik Youn ,  Adrian Ong ,  Sooho Cha ,  Chan-kyung Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C7/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2207/063

摘要： Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

摘要翻译： 示例实施例包括包括差分输出端子，直接耦合到预充电晶体管的第一和第二输入端子，预充电晶体管和电流调制晶体管的电阻型存储电流读出放大器电路。 预充电配置提供高峰值电流，以在电流检测放大器电路的“准备”或“预充电”阶段期间为位线和参考线充电。 电流调制晶体管被配置为在至少“设置”或“放大”阶段期间以饱和区域模式工作。 电流调制晶体管在“设置”或“放大”级期间连续平均位线电流和参考线电流，从而提高电路的抗噪声能力。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。