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    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SAME 审中-公开
    三维非易失性存储器件，存储器系统及其制造方法

    公开(公告)号：US20130153979A1

    公开(公告)日：2013-06-20

    申请号：US13605982

    申请日：2012-09-06

    申请人： Yoo Hyun NOH ,  Jong Moo Choi ,  Young Soo Ahn

    发明人： Yoo Hyun NOH ,  Jong Moo Choi ,  Young Soo Ahn

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/11578 ,  H01L21/266 ,  H01L27/11582

    摘要： A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.

    摘要翻译： 三维（3-D）非易失性存储器件包括通道结构，每个通道结构包括在衬底上堆叠并在第一方向上延伸的沟道层，其中沟道层分别包括阱区，位于彼此并且彼此间隔开的垂直栅极 在通道结构之间以及在通道层的阱区域上接触并沿与通道结构交叉的第二方向延伸的阱拾取线。

    Virtual system and method of analyzing operation of virtual system
    2.
    发明授权
    Virtual system and method of analyzing operation of virtual system 有权
    分析虚拟系统运行的虚拟系统和方法

    公开(公告)号：US08887139B2

    公开(公告)日：2014-11-11

    申请号：US12911997

    申请日：2010-10-26

    申请人： Mi-Kyoung Park ,  Jong Moo Choi ,  Jong Hwa Kim ,  Hee Kwon Park

    发明人： Mi-Kyoung Park ,  Jong Moo Choi ,  Jong Hwa Kim ,  Hee Kwon Park

    IPC分类号： G06F9/44 ,  G06F9/455

    CPC分类号： G06F9/45533 ,  G06F9/45554

    摘要： A virtual system comprises hardware, a virtualization layer virtualizing the hardware, a virtual machine monitor, a user domain operating using the virtualized hardware, and a root domain operating using the virtualized hardware and managing the user domain. The virtual machine monitor analyzes an operation performed by the user domain in real time and stores resulting analysis information in the root domain.

    摘要翻译： 虚拟系统包括硬件，虚拟化硬件虚拟化层，虚拟机监视器，使用虚拟化硬件操作的用户域，以及使用虚拟化硬件操作的根域并管理用户域。 虚拟机监视器实时分析用户域执行的操作，并将根据域存储结果分析信息。

    Flash memory device and method for manufacturing the same
    3.
    发明授权
    Flash memory device and method for manufacturing the same 有权
    闪存装置及其制造方法

    公开(公告)号：US06239009B1

    公开(公告)日：2001-05-29

    申请号：US09409677

    申请日：1999-09-30

    申请人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

    发明人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

    IPC分类号： H01L213205

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

    摘要： A flash memory device has improved erasable characteristics and device reliability. The flash memory device includes a semiconductor substrate and heavily doped impurity regions formed spaced apart from one another by a predetermined distance in the semiconductor substrate in a first direction. First and second isolation regions are formed spaced apart from each other by a second predetermined distance on the semiconductor substrate, in a second direction which is preferably at a right angle to the first direction. Each of the floating gates are formed between the first and second isolation regons and between the heavily doped impurity regions. The control gate lines are formed between the first and second isolation regions, and over the floating gates in the same direction as the first and second isolation regions. An erase gate line is formed to have a narrower width than the floating gate, and is formed over the floating gate, preferably at a right angle to the control gate line.

    摘要翻译： 闪存器件具有改进的可擦除特性和器件可靠性。 闪速存储器件包括在第一方向上在半导体衬底中彼此间隔开预定距离形成的半导体衬底和重掺杂杂质区。 第一隔离区域和第二隔离区域在第二方向上在半导体衬底上彼此间隔开第二预定距离，优选地与第一方向成直角。 每个浮置栅极形成在第一和第二隔离晶体之间以及重掺杂杂质区之间。 控制栅极线形成在第一和第二隔离区域之间，并且在与第一和第二隔离区域相同的方向上在浮动栅极上形成。 擦除栅极线形成为具有比浮动栅极窄的宽度，并且形成在浮动栅极上，优选地与控制栅极线成直角。

    Semiconductor memory cell and process for formation thereof
    4.
    发明授权
    Semiconductor memory cell and process for formation thereof 失效
    半导体存储单元及其形成工艺

    公开(公告)号：US5650957A

    公开(公告)日：1997-07-22

    申请号：US730256

    申请日：1996-10-15

    申请人： Jong Moo Choi

    发明人： Jong Moo Choi

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  G11C11/404

    CPC分类号： H01L27/1082 ,  H01L27/1203

    摘要： A semiconductor memory cell and a process for formation thereof is disclosed. A capacitor is disposed below a transistor, so that a DRAM cell that may be suitable for a high density semiconductor device is produced. A semiconductor device according to the present invention includes: a buried capacitor consisting of a storage electrode, a dielectric layer and a plate electrode formed on a substrate in a planar form; and a transistor formed above the capacitor, a source/drain region of the transistor being connected to the storage electrode of the capacitor.

    摘要翻译： 公开了一种半导体存储单元及其形成工艺。 电容器设置在晶体管的下方，从而制造可适用于高密度半导体器件的DRAM单元。 根据本发明的半导体器件包括：由平面形式形成在基板上的存储电极，电介质层和平板电极组成的埋入电容器; 以及形成在电容器上方的晶体管，晶体管的源极/漏极区域连接到电容器的存储电极。

    METHOD AND APPARATUS FOR POWER LOSS RECOVERY IN A FLASH MEMORY-BASED SSD
    5.
    发明申请
    METHOD AND APPARATUS FOR POWER LOSS RECOVERY IN A FLASH MEMORY-BASED SSD 有权
    用于基于闪存存储器的SSD中的电力损失恢复的方法和装置

    公开(公告)号：US20140229767A1

    公开(公告)日：2014-08-14

    申请号：US14346500

    申请日：2012-08-31

    申请人： Soo Yong Kang ,  You Jip Won ,  Jae Hyuk Cha ,  Dong Wook Kim ,  Sung Roh Yoon ,  Jong Moo Choi

    发明人： Soo Yong Kang ,  You Jip Won ,  Jae Hyuk Cha ,  Dong Wook Kim ,  Sung Roh Yoon ,  Jong Moo Choi

    IPC分类号： G06F11/30 ,  G06F12/02 ,  G06F11/16

    CPC分类号： G06F11/3062 ,  G06F11/1435 ,  G06F11/1441 ,  G06F11/1662 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/401 ,  G06F2212/7207

    摘要： The present invention relates to a storage device that uses a flash memory that performs power loss recovery, and to a method of power loss recovery by using the storage device using the flash memory. The storage device stores change information on metadata in physical pages in which one or more logical pages are compressed and stored. The change information on the metadata is information representing how the metadata is changed in association with data in the one or more logical pages. The storage device may synchronize the metadata in the flash memory and recover the metadata by applying the change information on the metadata to the synchronized metadata when a power supply is disrupted.

    摘要翻译： 本发明涉及使用进行功率损耗恢复的闪速存储器的存储装置，以及使用使用闪速存储器的存储装置的功率损耗恢复方法。 存储装置将关于一个或多个逻辑页面被压缩和存储的物理页面中的元数据的变更信息存储起来。 关于元数据的改变信息是表示元数据如何与一个或多个逻辑页面中的数据相关联地变化的信息。 存储设备可以使闪存中的元数据同步，并且当电源中断时，通过将元数据上的改变信息应用于同步的元数据来恢复元数据。

    Flash memory device and method for manufacturing the same
    7.
    发明授权
    Flash memory device and method for manufacturing the same 失效
    闪存装置及其制造方法

    公开(公告)号：US5986303A

    公开(公告)日：1999-11-16

    申请号：US911351

    申请日：1997-08-07

    申请人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

    发明人： Jong Moo Choi ,  Sung Ryul Kim ,  Young Keun Park

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L29/66825 ,  H01L27/115

    摘要： A flash memory device has improved erasable characteristics and device reliability. The flash memory device includes a semiconductor substrate and heavily doped impurity regions formed spaced apart from one another by a predetermined distance in the semiconductor substrate in a first direction. First and second isolation regions are formed spaced apart from each other by a second predetermined distance on the semiconductor substrate, in a second direction which is preferably at a right angle to the first direction. Each of the floating gates are formed between the first and second isolation regons and between the heavily doped impurity regions. The control gate lines are formed between the first and second isolation regions, and over the floating gates in the same direction as the first and second isolation regions. An erase gate line is formed to have a narrower width than the floating gate, and is formed over the floating gate, preferably at a right angle to the control gate line.

    摘要翻译： 闪存器件具有改进的可擦除特性和器件可靠性。 闪速存储器件包括在第一方向上在半导体衬底中彼此间隔开预定距离形成的半导体衬底和重掺杂杂质区。 第一隔离区域和第二隔离区域在第二方向上在半导体衬底上彼此间隔开第二预定距离，优选地与第一方向成直角。 每个浮置栅极形成在第一和第二隔离晶体之间以及重掺杂杂质区之间。 控制栅极线形成在第一和第二隔离区域之间，并且在与第一和第二隔离区域相同的方向上在浮动栅极上形成。 擦除栅极线形成为具有比浮动栅极窄的宽度，并且形成在浮动栅极上，优选地与控制栅极线成直角。