公开(公告)号：US07808046B2

公开(公告)日：2010-10-05

申请号：US11448299

申请日：2006-06-07

申请人： Yoon Sung Lee ,  Kook Whee Kwak

发明人： Yoon Sung Lee ,  Kook Whee Kwak

IPC分类号： H01L23/62

CPC分类号： H01L29/41758 ,  H01L27/0266 ,  H01L29/78

摘要： The electrostatic protection device includes a semiconductor substrate having a well formed therein. At least two sets of transistor fingers, for example the NMOS type, are spaced apart from each other. Each set of the MOS fingers includes multiple gates arranged in parallel to each other in one direction, and sources and drains alternately arranged at both sides of the gates in the semiconductor substrate. A well pickup surrounding every set of the transistor fingers and extending between any two set of the fingers is formed. Metal wires are connected to at least two portions of each of the drains and are also connected to an input/output pad to which Electrostatic Discharge (ESD) excessive current is introduced.

摘要翻译： 静电保护装置包括其中良好地形成的半导体衬底。 至少两组晶体管指，例如NMOS型，彼此间隔开。 每组MOS指状物包括在一个方向上彼此平行布置的多个栅极，并且交替地布置在半导体衬底中的栅极的两侧的源极和漏极。 形成围绕每组晶体管指并且在任意两组指状物之间延伸的阱拾取器。 金属线连接到每个漏极的至少两个部分，并且还连接到引入静电放电（ESD）过电流的输入/输出焊盘。

公开(公告)号：US20080247104A1

公开(公告)日：2008-10-09

申请号：US12062722

申请日：2008-04-04

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： The present invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit of the present invention includes a transfer unit that transfers electrostaticity from at least one of a plurality of input/output pads to a boost bus line, a trigger unit that responds to the electrostaticity transferred via the boost bus line to detect a trigger voltage and apply it to a trigger bus line, and a plurality of clamp units that are connected between the input/output pads and an internal circuit. The clamp units are triggered by the trigger voltage of the trigger unit to discharge electrostaticity of the input/output pads to a first or second power supply voltage line, thereby safely protecting the internal circuit from electrostatic damage and lowering the operating voltage of the clamp unit with minimum costs without increasing an area of the electrostatic discharge protective circuit within a semiconductor integrated circuit.

摘要翻译： 本发明公开了一种静电放电保护电路。 本发明的静电放电保护电路包括将静电从多个输入/输出焊盘传递到升压总线的转移单元，响应经由升压总线传输的静电以检测 触发电压并将其施加到触发总线，以及连接在输入/输出焊盘和内部电路之间的多个钳位单元。 夹紧单元由触发单元的触发电压触发，以将输入/输出焊盘的静电放电到第一或第二电源电压线，从而安全地保护内部电路免受静电损坏并降低钳位单元的工作电压 以最小的成本，而不增加半导体集成电路内的静电放电保护电路的面积。

公开(公告)号：US20120292737A1

公开(公告)日：2012-11-22

申请号：US13566588

申请日：2012-08-03

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H01L29/861

CPC分类号： H01L29/8611 ,  H01L29/417

摘要： A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

摘要翻译： 二极管包括在半导体衬底中形成的P型阱，形成在P型阱中的至少一个N型杂质掺杂区，形成为围绕N型杂质掺杂区的隔离区，P型杂质 形成为围绕隔离区域的掺杂区域，以单行或多行形式形成在N型杂质掺杂区域中的第一触点，以及在单行或多个行中形成在P型杂质掺杂区域中的第二触点 行，其中可以通过改变N型杂质掺杂区域和P型杂质掺杂区域之间的距离，第一触点之间的接触间距和第二触点之间的接触间距来调节引脚电阻。

公开(公告)号：US20120119320A1

公开(公告)日：2012-05-17

申请号：US13359744

申请日：2012-01-27

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H01L29/02

CPC分类号： H01L29/8611 ,  H01L29/417

摘要： A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

公开(公告)号：US08050003B2

公开(公告)日：2011-11-01

申请号：US12062722

申请日：2008-04-04

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： The present invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit of the present invention includes a transfer unit that transfers electrostaticity from at least one of a plurality of input/output pads to a boost bus line, a trigger unit that responds to the electrostaticity transferred via the boost bus line to detect a trigger voltage and apply it to a trigger bus line, and a plurality of clamp units that are connected between the input/output pads and an internal circuit. The clamp units are triggered by the trigger voltage of the trigger unit to discharge electrostaticity of the input/output pads to a first or second power supply voltage line, thereby safely protecting the internal circuit from electrostatic damage and lowering the operating voltage of the clamp unit with minimum costs without increasing an area of the electrostatic discharge protective circuit within a semiconductor integrated circuit.

摘要翻译： 本发明公开了一种静电放电保护电路。 本发明的静电放电保护电路包括将静电从多个输入/输出焊盘传递到升压总线的转移单元，响应经由升压总线传输的静电以检测 触发电压并将其施加到触发总线，以及连接在输入/输出焊盘和内部电路之间的多个钳位单元。 夹紧单元由触发单元的触发电压触发，以将输入/输出焊盘的静电放电到第一或第二电源电压线，从而安全地保护内部电路免受静电损坏并降低钳位单元的工作电压 以最小的成本，而不增加半导体集成电路内的静电放电保护电路的面积。

公开(公告)号：US07876541B2

公开(公告)日：2011-01-25

申请号：US12611212

申请日：2009-11-03

申请人： Jung Eon Moon ,  Dae Gwan Kang ,  Kook Whee Kwak ,  Nak Heon Choi ,  Si Woo Lee ,  Hee Jeong Son ,  Yun Suk ,  Seong Hoon Jeong ,  Joon Won Lee

发明人： Jung Eon Moon ,  Dae Gwan Kang ,  Kook Whee Kwak ,  Nak Heon Choi ,  Si Woo Lee ,  Hee Jeong Son ,  Yun Suk ,  Seong Hoon Jeong ,  Joon Won Lee

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

摘要翻译： 静电放电（ESD）保护电路保护内部电路中元件的栅极氧化物免受ESD影响。 在ESD测试期间，如果连接在电源焊盘和接地焊盘之间的ESD保护器的驱动电压的总和高于内部电路中的元件的栅极氧化物击穿电压，则ESD保护器的结构被改变，或者另一个ESD保护器 另外设置为保护内部电路中的元件的栅极氧化物免于ESD。

公开(公告)号：US07616415B2

公开(公告)日：2009-11-10

申请号：US11735038

申请日：2007-04-13

申请人： Jung Eon Moon ,  Dae Gwan Kang ,  Kook Whee Kwak ,  Nak Heon Choi ,  Si Woo Lee ,  Hee Jeong Son ,  Suk Yun ,  Seong Hoon Jeong ,  Joon Won Lee

发明人： Jung Eon Moon ,  Dae Gwan Kang ,  Kook Whee Kwak ,  Nak Heon Choi ,  Si Woo Lee ,  Hee Jeong Son ,  Suk Yun ,  Seong Hoon Jeong ,  Joon Won Lee

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection circuit protects a gate oxide of elements in an internal circuit against ESD. During an ESD test, if the sum of driving voltages of ESD protectors connected between a power pad and a ground pad is higher than the gate oxide breakdown voltage of elements in the internal circuit, the structure of the ESD protector is changed or another ESD protector is additionally provided so as to protect the gate oxide of the elements in the internal circuit against ESD.

摘要翻译： 静电放电（ESD）保护电路保护内部电路中元件的栅极氧化物免受ESD影响。 在ESD测试期间，如果连接在电源焊盘和接地焊盘之间的ESD保护器的驱动电压的总和高于内部电路中的元件的栅极氧化物击穿电压，则ESD保护器的结构被改变，或者另一个ESD保护器 另外设置为保护内部电路中的元件的栅极氧化物免于ESD。

公开(公告)号：US08373255B2

公开(公告)日：2013-02-12

申请号：US13566588

申请日：2012-08-03

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H01L29/06

CPC分类号： H01L29/8611 ,  H01L29/417

摘要： A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

摘要翻译： 二极管包括在半导体衬底中形成的P型阱，形成在P型阱中的至少一个N型杂质掺杂区，形成为围绕N型杂质掺杂区的隔离区，P型杂质 形成为围绕隔离区域的掺杂区域，以单行或多行形式形成在N型杂质掺杂区域中的第一触点，以及在单行或多个行中形成在P型杂质掺杂区域中的第二触点 行，其中可以通过改变N型杂质掺杂区域和P型杂质掺杂区域之间的距离，第一触点之间的接触间距和第二触点之间的接触间距来调节引脚电阻。

公开(公告)号：US08253223B2

公开(公告)日：2012-08-28

申请号：US13359744

申请日：2012-01-27

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H01L29/06

CPC分类号： H01L29/8611 ,  H01L29/417

摘要： A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

摘要翻译： 二极管包括在半导体衬底中形成的P型阱，形成在P型阱中的至少一个N型杂质掺杂区，形成为围绕N型杂质掺杂区的隔离区，P型杂质 形成为围绕隔离区域的掺杂区域，以单行或多行形式形成在N型杂质掺杂区域中的第一触点，以及在单行或多个行中形成在P型杂质掺杂区域中的第二触点 行，其中可以通过改变N型杂质掺杂区域和P型杂质掺杂区域之间的距离，第一触点之间的接触间距和第二触点之间的接触间距来调节引脚电阻。

公开(公告)号：US07838941B2

公开(公告)日：2010-11-23

申请号：US11963910

申请日：2007-12-24

申请人： Kook Whee Kwak

发明人： Kook Whee Kwak

IPC分类号： H01L29/72

CPC分类号： H01L27/0266

摘要： Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.

摘要翻译： 公开了一种具有低触发电压并保护内部电路免受静电放电的静电放电保护装置。 ESD保护装置包括NMOS晶体管，其中第一焊盘和漏极彼此连接，第二焊盘和源彼此连接。 一个电容器，其端部连接到第一焊盘，另一端连接到NMOS晶体管的栅极和NMOS晶体管的衬底接触。 ESD保护器件还包括电阻器，其中端部连接到第二焊盘，另一端连接到电容器。 第一焊盘可以是电源焊盘，第二焊盘可以是接地焊盘。 或者，第一焊盘可以是输入/输出焊盘，第二焊盘可以是接地焊盘。