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公开(公告)号：US08018784B2
公开(公告)日：2011-09-13
申请号：US12636528
申请日：2009-12-11
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。 Ina数据处理器具有总线控制器，其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，时序控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令，使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器， 响应于针对外围电路的写入指令，使定时控制电路开始与高速时钟信号的周期同步地写入外围电路，并且与该时钟信号同步地终止写入 周期的低速时钟信号。
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公开(公告)号：US20100182848A1
公开(公告)日：2010-07-22
申请号：US12636528
申请日：2009-12-11
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。 Ina数据处理器具有总线控制器，其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，定时控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令，使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器， 响应于针对外围电路的写入指令，使定时控制电路开始与高速时钟信号的周期同步地写入外围电路，并且与该时钟信号同步地终止写入 周期的低速时钟信号。
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公开(公告)号：US08531893B2
公开(公告)日：2013-09-10
申请号：US13674043
申请日：2012-11-11
IPC分类号： G11C7/10
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。
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公开(公告)号：US08339869B2
公开(公告)日：2012-12-25
申请号：US13220747
申请日：2011-08-30
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译： 提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。 在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路 在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器 速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与 低速时钟信号的周期。
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公开(公告)号：US20090015590A1
公开(公告)日：2009-01-15
申请号：US12237112
申请日：2008-09-24
IPC分类号： G06T15/00
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US07868892B2
公开(公告)日：2011-01-11
申请号：US12237112
申请日：2008-09-24
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中用于绘制和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US20050030311A1
公开(公告)日：2005-02-10
申请号：US10891047
申请日：2004-07-15
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US07446775B2
公开(公告)日：2008-11-04
申请号：US10891047
申请日：2004-07-15
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US09030570B2
公开(公告)日：2015-05-12
申请号：US13529642
申请日：2012-06-21
摘要： A parallel operation histogramming device can handle parallel-input data from a plurality of processors to generate frequency data of a histogram. The processing time for generating frequency data of the histogram is independent of the distribution of histogram values in the input data. The device can also reduce the memory area used for accumulating frequency data of the histogram. The device includes a histogram counter circuit which has a plurality of counters equal in number to the number of histogram bins. The counters count in parallel the number of pieces of data for each type of the operation results from the plurality of processors. The counted values from each counter are accumulated to form the frequencies in a histogram.
摘要翻译： 并行操作直方图设备可以处理来自多个处理器的并行输入数据，以产生直方图的频率数据。 用于生成直方图的频率数据的处理时间与输入数据中直方图值的分布无关。 该装置还可以减少用于累积直方图的频率数据的存储区域。 该装置包括直方图计数器电路，该电路具有与直方图数目的数量相等的多个计数器。 计数器并行计数来自多个处理器的每种类型的操作结果的数据块数。 累积每个计数器的计数值以形成直方图中的频率。
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公开(公告)号：US09367315B2
公开(公告)日：2016-06-14
申请号：US12917840
申请日：2010-11-02
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0673 , G06F9/30087 , G06K9/00805
摘要： Provided is an image processing device capable of an image processing with using a general-purpose image processing hardware in accordance with video input without mediation of a CPU. The image processing device includes: a storage medium for storing an image data acquired by video inputting unit for acquiring video images; a CPU for a general processing; image processing unit for processing the image data stored in the storage medium; setting unit for determining a processing content of the image processing unit; a command list indicating an order of setting and activating the image processing unit; and command writing unit for setting and activating the image processing unit based on the command list in synchronization with input of the image data from the video inputting unit without mediation of the CPU.
摘要翻译： 提供了一种图像处理装置，其能够根据视频输入而使用通用图像处理硬件进行图像处理，而无需中介CPU。 该图像处理装置包括：存储介质，用于存储由用于获取视频图像的视频输入单元获取的图像数据; 用于一般处理的CPU; 图像处理单元，用于处理存储在存储介质中的图像数据; 设置单元，用于确定图像处理单元的处理内容; 指示设置和激活图像处理单元的顺序的命令列表; 以及命令写入单元，用于根据来自视频输入单元的图像数据的输入同步地基于命令列表设置和激活图像处理单元，而无需CPU的中介。
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