公开(公告)号：US06490657B1

公开(公告)日：2002-12-03

申请号：US08917530

申请日：1997-08-26

申请人： Yoshio Masubuchi ,  Takuya Kano ,  Hiroshi Sakai

发明人： Yoshio Masubuchi ,  Takuya Kano ,  Hiroshi Sakai

IPC分类号： G06F1208

CPC分类号： G06F11/2041 ,  G06F11/1407 ,  G06F11/2043 ,  G06F12/0804 ,  G06F12/0831

摘要： Addresses of all of dirty blocks of a cache memory are, by an update address registering section, stored in one of plural regions of an update address memory. When a certain cache block is brought to a dirty state and then suspended from the dirty state, the update address removing section removes the address from the region. When cache flush is performed, a flush executing section sequentially fetches the addresses of the dirty blocks from each region to issue, to the system bus, a command for writing-back data indicated by the address into the main memory so that the contents of all of the a dirty block are written-back into the main memory. Therefore, the cache flush apparatus according to the present invention is able to shorten time required to perform the cache flush procedure and to improve the performance of a computer system having the cache flush apparatus.

摘要翻译： 通过更新地址登记部存储在更新地址存储器的多个区域中的一个区域中的高速缓冲存储器的所有脏块的地址。 当某个缓存块处于脏状态，然后从脏状态暂停时，更新地址删除部分从该区域中删除该地址。 当执行缓存刷新时，刷新执行部分从每个区域顺序地提取脏块的地址，以向系统总线发出用于将由地址指示的数据写回到主存储器中的命令，使得所有内容 的脏块被写回主内存。 因此，根据本发明的高速缓存清理装置能够缩短执行高速缓存刷新过程所需的时间并且能够提高具有高速缓存清理装置的计算机系统的性能。

公开(公告)号：US5828821A

公开(公告)日：1998-10-27

申请号：US665542

申请日：1996-06-18

申请人： Satoshi Hoshina ,  Hiroshi Sakai ,  Hideaki Hirayama ,  Shigefumi Ohmori ,  Takahiro Fujii ,  Yoshio Masubuchi

发明人： Satoshi Hoshina ,  Hiroshi Sakai ,  Hideaki Hirayama ,  Shigefumi Ohmori ,  Takahiro Fujii ,  Yoshio Masubuchi

IPC分类号： G06F15/16 ,  G06F11/14 ,  G06F12/08 ,  G06F15/177 ,  G06F11/34

CPC分类号： G06F11/1458 ,  G06F12/0806 ,  G06F2201/82

摘要： Log memories for recording updated history of a main memory are provided. CPUs record the updated history of the main memory to either of the log memories and writes context thereof and content of a cache memory to the main memory at a checkpoint acquisition. The updated history of the main memory is switched from one of CPUs that has finished a checkpoint processing to other one of the log memories in which the CPUs do not use to record the updated history of the main memory. Normal processing is restarted without waiting for finishing the checkpoint acquisition of the other ones of CPUs.

摘要翻译： 提供用于记录主存储器更新历史记录的日志记忆。 CPU在检查点获取时将主存储器的更新历史记录到任一记录存储器，并将其上下文和缓存存储器的内容写入主存储器。 主存储器的更新历史从已经完成检查点处理的一个CPU切换到CPU不用于记录主存储器的更新历史的其他日志存储器中。 正常处理重新启动，而不等待完成其他CPU的检查点获取。

公开(公告)号：US5537569A

公开(公告)日：1996-07-16

申请号：US204499

申请日：1994-03-02

申请人： Yoshio Masubuchi

发明人： Yoshio Masubuchi

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F15/177

CPC分类号： G06F12/0826

摘要： In a shared memory type multiprocessing system, when data stored in each processing element is managed in a directory method, a plurality of processing elements are grouped in advance. A directory memory is provided along with a data memory mounted in a shared memory. Directory information held in the directory memory indicates which one of the groups holds a copy of a data block. In response to a request from the processing element, the shared memory executes a process of finding the processing element from the processing group, or a process of finding the processing group from the processing element.

摘要翻译： 在共享存储器型多处理系统中，当以目录方法管理存储在每个处理元件中的数据时，预先对多个处理元件进行分组。 目录存储器与安装在共享存储器中的数据存储器一起提供。 保存在目录存储器中的目录信息指示哪个组保存数据块的副本。 响应于来自处理元件的请求，共享存储器执行从处理组找到处理元件的处理，或从处理元件发现处理组的处理。

公开(公告)号：US06367076B1

公开(公告)日：2002-04-02

申请号：US09266872

申请日：1999-03-12

申请人： Toru Imai ,  Hiroko Fujii ,  Yoshio Masubuchi

发明人： Toru Imai ,  Hiroko Fujii ,  Yoshio Masubuchi

IPC分类号： G06F945

CPC分类号： G06F9/30189 ,  G06F8/447 ,  G06F9/30072

摘要： A compiling method, for compiling a source program into an object program for a CPU having multiple functional units that allow for concurrent operations and supporting predicated execution, for generating the object program that can be executed on the CPU at high speed by analyzing the source program and generating intermediate codes, making an analysis of the intermediate codes, generating, based on the analysis, an execution mode set instruction to set an execution mode managed within the CPU, allocating, based on the analysis, instructions such that whether they are to be executed or not to be executed depends on the execution mode set by the execution mode set instruction from the intermediate codes, wherein one or more instructions in which values in their respective specific fields are identical make an block together for every value in the specific field, finding, for each block, an ending part of the block in which its last instruction is allocated, and generating, when the ending part of a certain block is to be earlier in the object program than the ending part of another block, an unconditional branch instruction identical in specific field value to the instructions in the certain block, and allocating it either to be executed in the ending part of the certain block or to be executed as immediately as possible after the ending part of the block.

摘要翻译： 一种编译方法，用于将源程序编译成具有允许并发操作和支持预定执行的多个功能单元的CPU的对象程序，用于通过分析源程序来生成可以在CPU上高速执行的对象程序 以及生成中间代码，对中间代码进行分析，基于分析生成执行模式设置指令，以设置在CPU内管理的执行模式，基于分析分配指令，以便它们是否将被 执行或不执行取决于由来自中间代码的执行模式设置指令设置的执行模式，其中其各自特定字段中的值相同的一个或多个指令对于特定字段中的每个值进行块合并， 发现对于每个块，分配其最后指令的块的结束部分，并且当en 某个块的一部分在目标程序中比在另一个块的结束部分更早，一个与特定字段值相同的特定字段值的无条件转移指令与该特定块中的指令相同，并且将其分配给在结束部分中执行 或者在块的结束部分之后尽快地执行该块。

公开(公告)号：US5745730A

公开(公告)日：1998-04-28

申请号：US653909

申请日：1996-05-28

申请人： Hiroshi Nozue ,  Yoshio Masubuchi

发明人： Hiroshi Nozue ,  Yoshio Masubuchi

IPC分类号： G06F11/14 ,  G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0831

摘要： A bus interface is connected to a system bus for monitoring a bus command indicating that data is updated on a cache memory of a processor. If the data is updated on the cache memory, the external tag storage device stores state information to indicate the update of the data and a physical address corresponding to the updated data. An external tag reading device reads the state information stored in the external tag storage device, when the updated data on the cache memory is stored in a main memory. A bus command for flushing the updated data from the cache memory to the main memory is generated, based on the state of the tag read out from the external tag storage device. An invalid bus command generation device outputs an invalid bus command to the system bus through a FIFO.

摘要翻译： 总线接口连接到系统总线，用于监视指示在处理器的高速缓冲存储器上更新数据的总线命令。 如果在高速缓冲存储器上更新数据，则外部标签存储装置存储指示更新数据的状态信息和对应于更新数据的物理地址。 当高速缓冲存储器上的更新数据存储在主存储器中时，外部标签读取装置读取存储在外部标签存储装置中的状态信息。 基于从外部标签存储装置读出的标签的状态，生成用于将更新的数据从高速缓冲存储器刷新到主存储器的总线命令。 无效总线命令生成装置通过FIFO向系统总线输出无效总线命令。

公开(公告)号：US5530817A

公开(公告)日：1996-06-25

申请号：US20836

申请日：1993-02-22

申请人： Yoshio Masubuchi

发明人： Yoshio Masubuchi

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/34 ,  G06F9/38 ,  G06F9/28 ,  G06F13/38

CPC分类号： G06F9/3885 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3891

摘要： Disclosed is a very large instruction word (VLIW) type parallel processing computer architecture. The VLIW is divided into operation field groups which are made up of operands. Each operand in a VLIW is executed by a different processor. The computer contains independent register files for each of the respective operation field groups in a single instruction word. Data transfer between the registers is executed via signal lines which connect registers that are designated as operands in each operation field group to each other. The data transfer between register files is directed by a command which is included as an operand for one of the processors. This command eliminates the need for a destination field in each operand simplifying the VLIW.

摘要翻译： 公开了一种非常大的指令字（VLIW）型并行处理计算机体系结构。 VLIW分为由操作数组成的操作字段组。 VLIW中的每个操作数由不同的处理器执行。 计算机在单个指令字中包含用于每个相应操作区组的独立寄存器文件。 寄存器之间的数据传输是通过将每个操作字段组中被指定为操作数的寄存器相互连接的信号线来执行的。 寄存器文件之间的数据传输由作为处理器之一的操作数包含的命令引导。 该命令消除了对每个操作数中的目标字段的需要，从而简化了VLIW。

公开(公告)号：US6148416A

公开(公告)日：2000-11-14

申请号：US853867

申请日：1997-05-09

申请人： Yoshio Masubuchi

发明人： Yoshio Masubuchi

IPC分类号： G06F11/14 ,  G06F11/00

CPC分类号： G06F11/1407

摘要： A before-image buffer controller is arranged separately from a memory controller and is connected to a system bus. When there is a write access request from a CPU to a cache memory corresponding to this CPU, the before-image buffer controller is automatically started in response to a command issued from this cache memory onto the system bus, and issues a command for reading previous data from a main memory. Since the before-image buffer controller operable independently of the memory controller is arranged in this way, a memory state restore function can be easily realized by using an existing computer system as it is without changing a memory controller.

摘要翻译： 前映像缓冲器控制器与存储器控制器分开布置并连接到系统总线。 当存在从CPU到与该CPU相对应的高速缓冲存储器的写入访问请求时，响应于从该高速缓存存储器发出到系统总线的命令，自动启动前映像缓冲器控制器，并且发出读取前一个 来自主内存的数据。 由于以这种方式布置可独立于存储器控制器操作的前图像缓冲器控制器，所以可以通过使用现有的计算机系统来容易地实现存储器状态恢复功能，而不改变存储器控制器。

公开(公告)号：US06079030A

公开(公告)日：2000-06-20

申请号：US317915

申请日：1999-05-25

申请人： Yoshio Masubuchi

发明人： Yoshio Masubuchi

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/14 ,  G06F12/08 ,  G06F15/177

CPC分类号： G06F11/1407 ,  G06F12/0831

摘要： In a memory state recovering apparatus, processors process data and a main memory holds data necessary for the data processing at the processors. Caches are provided to correspond to the processors and have the function of issuing an invalidation transaction to specify the invalidation of the data to maintain the consistency of the data. A before image buffer combines an address in the main memory with the data held in the location indicated by the address and stores the combination. A memory access control section stores in the buffer memory the address targeted in the main memory and the data stored in the location indicated by the address in accordance with the invalidation transaction issued from the caches. With this configuration, the time required for a checkpoint process can be shortened, thereby improving the system performance.

摘要翻译： 在存储器状态恢复装置中，处理器处理数据，并且主存储器保存处理器处的数据处理所必需的数据。 缓存被提供以对应于处理器，并且具有发出无效事务以指定数据的无效的功能以维持数据的一致性。 前图像缓冲器将主存储器中的地址与由地址指示的位置保存的数据组合，并存储组合。 存储器访问控制部分根据从高速缓存发出的无效化事务将存储在主存储器中的地址和存储在由地址指示的位置的数据存储在缓冲存储器中。 利用该配置，可以缩短检查点处理所需的时间，从而提高系统性能。

公开(公告)号：US5913021A

公开(公告)日：1999-06-15

申请号：US665628

申请日：1996-06-18

申请人： Yoshio Masubuchi

发明人： Yoshio Masubuchi

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/14 ,  G06F12/08 ,  G06F15/177 ,  G06F11/20

CPC分类号： G06F11/1407 ,  G06F12/0831

摘要： In a memory state recovering apparatus, processors process data and a main memory holds data necessary for the data processing at the processors. Caches are provided to correspond to the processors and have the function of issuing an invalidation transaction to specify the invalidation of the data to maintain the consistency of the data. A before image buffer combines an address in the main memory with the data held in the location indicated by the address and stores the combination. A memory access control section stores in the buffer memory the address targeted in the main memory and the data stored in the location indicated by the address in accordance with the invalidation transaction issued from the caches. With this configuration, the time required for a checkpoint process can be shortened, thereby improving the system performance.

公开(公告)号：US4947365A

公开(公告)日：1990-08-07

申请号：US222255

申请日：1988-07-21

申请人： Yoshio Masubuchi

发明人： Yoshio Masubuchi

IPC分类号： G01C21/00 ,  G06F17/50

CPC分类号： G06F17/509 ,  G06F17/5031

摘要： A path trace apparatus according to this invention for tracing path having specified start, middle and end points in a network comprises means for tracing a path in a forward direction from the middle point to the end point based on data representing the coupling relationship between elements constituting the network, and means for tracing a path in a reverse direction from the middle point to the start point based on the data. In tracing a path in a network by specifying three points, signal paths are traced in the forward and reverse directions with the middle point as the center, thus eliminating the wasteful tracing of paths which do not pass the middle point and thereby significantly increasing the tracing efficiency.

摘要翻译： 根据本发明的用于在网络中具有指定的开始，中间和终点的跟踪路径的路径跟踪装置包括用于基于表示构成的元素之间的耦合关系的数据的从中点到终点跟踪前向路径的装置 网络，以及用于根据数据从中点到起始点跟踪反向路径的装置。 在通过指定三个点来跟踪网络中的路径时，以中点为中心在前向和反向方向上跟踪信号路径，从而消除了不通过中间点的路径的浪费跟踪，从而显着增加跟踪 效率。