公开(公告)号：US07123054B2

公开(公告)日：2006-10-17

申请号：US10869328

申请日：2004-06-15

申请人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

发明人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

IPC分类号： H03K19/0175 ,  H03K19/094 ,  H03K17/16

CPC分类号： H01L27/0262

摘要： A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

摘要翻译： 半导体集成电路器件包括形成在半导体芯片中的半导体集成电路和形成在半导体芯片中并具有一端和另一端都连接到半导体集成电路的电流通路的开关元件。 开关元件接收由控制电路产生的控制信号，并且通过双极性操作使电流从电流路径的一端流到另一端。 半导体集成电路装置还包括形成在半导体芯片中并被配置为控制开关元件的电流路径的导通/非导通状态的控制电路。

公开(公告)号：US20050047042A1

公开(公告)日：2005-03-03

申请号：US10869328

申请日：2004-06-15

申请人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

发明人： Youichi Satou ,  Toshikazu Sei ,  Akira Yamaguchi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L27/10 ,  H02H3/00

CPC分类号： H01L27/0262

摘要： A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

摘要翻译： 半导体集成电路器件包括形成在半导体芯片中的半导体集成电路和形成在半导体芯片中并具有一端和另一端都连接到半导体集成电路的电流通路的开关元件。 开关元件接收由控制电路产生的控制信号，并且通过双极性操作使电流从电流路径的一端流到另一端。 半导体集成电路装置还包括形成在半导体芯片中并被配置为控制开关元件的电流路径的导通/非导通状态的控制电路。

公开(公告)号：USRE39469E1

公开(公告)日：2007-01-16

申请号：US09963735

申请日：2001-09-27

申请人： Nobuo Fudanuki ,  Toshikazu Sei

发明人： Nobuo Fudanuki ,  Toshikazu Sei

IPC分类号： H03K19/177

CPC分类号： H03K19/1735

摘要： The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.

摘要翻译： 本发明涉及一种半定制ASIC，其中布置有多个标准单元行。 门阵列中使用的标准单元和基本单元混合安装在同一芯片上。 各个单元行由具有空白空间的多个标准单元组成。 门阵列中使用的基本单元被布置为虚拟单元。 它们被布置在同一标准单元行中的标准单元之间的多个标准单元之间的布线沟道区域或空白空间中。 如果采用无通道型标准电池，则只能使用后者。 当需要改变电路设计或图案时，可以通过在栅极阵列基本单元上形成金属布线层来满足变化的要求。 由于可以在不改变栅极多晶硅区域和金属布线层下面的源极/漏极区域的情况下修改电路，因此可以在短时间内实现设计和制造。

公开(公告)号：US5272366A

公开(公告)日：1993-12-21

申请号：US747864

申请日：1991-08-20

申请人： Toshikazu Sei ,  Yasunori Tanaka ,  Hiroyuki Hara

发明人： Toshikazu Sei ,  Yasunori Tanaka ,  Hiroyuki Hara

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/732 ,  H01L27/10 ,  H01L29/76

CPC分类号： H01L27/11896

摘要： A bipolar transistor/insulated gate transistor hybrid semiconductor device comprises a well region formed on a semiconductor substrate to serve as a first active region of a bipolar transistor, an insulated gate transistor having source and drain regions formed in the well region, which acts as a back gate of the insulated gate transistor, and second and third active regions of the bipolar transistor formed in the well region. At least one of the second and third active regions is used in common to one of the source and drain regions of the insulated gate transistor. A plurality of well regions is regularly arranged to constitute a gate array.

摘要翻译： 双极晶体管/绝缘栅晶体管混合半导体器件包括形成在半导体衬底上的阱区，用作双极晶体管的第一有源区，在阱区中形成源区和漏区的绝缘栅晶体管，其作为 绝缘栅晶体管的背栅，以及形成在阱区中的双极晶体管的第二和第三有源区。 第二和第三有源区域中的至少一个共用于绝缘栅极晶体管的源极和漏极区域中的一个。 规则地布置多个阱区以构成栅极阵列。

公开(公告)号：US07759995B2

公开(公告)日：2010-07-20

申请号：US12253029

申请日：2008-10-16

申请人： Chihiro Ishii ,  Toshikazu Sei

发明人： Chihiro Ishii ,  Toshikazu Sei

IPC分类号： H03K3/286

CPC分类号： H03K3/0375 ,  H03K3/356156 ,  H03K3/356173

摘要： A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

摘要翻译： 半导体集成电路包括第一数据保持部，第一上拉电路，第一下拉电路，第一反馈电路和第二反馈电路。 第一数据保持部保存第一输出数据。 第一个上拉电路将输入数据作为上拉控制信号，当上拉控制信号取一个值时，拉起第一个输出数据。 第一个下拉电路将输入数据作为下拉控制信号，当下拉控制信号取另一个值时，拉下第一个输出数据。 第一反馈电路将对应于第一输出数据的第一反馈信号作为上拉控制信号反馈到第一上拉电路。 第二反馈电路将与第一输出数据对应的第二反馈信号作为下拉控制信号反馈到第一下拉电路。

公开(公告)号：US06690073B2

公开(公告)日：2004-02-10

申请号：US09819532

申请日：2001-03-27

申请人： Yasunobu Umemoto ,  Toshikazu Sei ,  Toshiki Morimoto ,  Hiroaki Suzuki

发明人： Yasunobu Umemoto ,  Toshikazu Sei ,  Toshiki Morimoto ,  Hiroaki Suzuki

IPC分类号： H01L2976

CPC分类号： H01L27/11807 ,  H01L27/0211

摘要： A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

摘要翻译： 描述了能够以更高的封装密度和小尺寸的标准电池结构制造的半导体集成电路。 在半导体集成电路中，衬底区域和源极区域被相邻标准单元以及位于分别从衬底区域的中心向内位移的公共接触区域共享。

公开(公告)号：US06271548B1

公开(公告)日：2001-08-07

申请号：US08859108

申请日：1997-05-20

申请人： Yasunobu Umemoto ,  Yukinori Uchino ,  Toshikazu Sei ,  Muneaki Maeno

发明人： Yasunobu Umemoto ,  Yukinori Uchino ,  Toshikazu Sei ,  Muneaki Maeno

IPC分类号： H01L2710

CPC分类号： H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.

摘要翻译： 提供了主切片布局技术来提高诸如ASIC之类的半导体集成电路的集成密度。 具体而言，在半导体芯片上配置有多个栅极基体单元，在栅极基体单元上形成具有不均匀间距的布线沟道栅格。 如果沿着布线通道格栅设计金属布线的布局，则可以将小型化图案设置为较小的值，同时保持预定金属布线（例如预选值的电源布线）的线宽。 由于金属布线层的布局的灵活性大，即使基本单元处理和布线处理的设计规则不同，也可以实现图案的小型化。

公开(公告)号：US06054872A

公开(公告)日：2000-04-25

申请号：US997035

申请日：1997-12-23

申请人： Nobuo Fudanuki ,  Toshikazu Sei

发明人： Nobuo Fudanuki ,  Toshikazu Sei

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/118 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1735

摘要： The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.

摘要翻译： 本发明涉及一种半定制ASIC，其中布置有多个标准单元行。 门阵列中使用的标准单元和基本单元混合安装在同一芯片上。 各个单元行由具有空白空间的多个标准单元组成。 门阵列中使用的基本单元被布置为虚拟单元。 它们被布置在同一标准单元行中的标准单元之间的多个标准单元之间的布线沟道区域或空白空间中。 如果采用无通道型标准电池，则只能使用后者。 当需要改变电路设计或图案时，可以通过在栅极阵列基本单元上形成金属布线层来满足变化的要求。 由于可以在不改变栅极多晶硅区域和金属布线层下面的源极/漏极区域的情况下修改电路，因此可以在短时间内实现设计和制造。

公开(公告)号：US20060199325A1

公开(公告)日：2006-09-07

申请号：US11365087

申请日：2006-02-28

申请人： Muneaki Maeno ,  Toshikazu Sei

发明人： Muneaki Maeno ,  Toshikazu Sei

IPC分类号： H01L21/8238 ,  H01L21/3205

CPC分类号： H01L27/11807

摘要： A semiconductor integrated circuit device includes cells, each of the cells including a gate electrode, which is provided on the well, and first diffusion layers of a second conductivity type which are provided in the well such that the first diffusion layers sandwich the gate electrode, the first diffusion layers functioning as sources/drains. The device further includes sub-regions which are arranged in a non-occupied area of the logic circuit structure region, each of the sub-regions including a conductive layer, which is provided on the well and has the same pattern shape as the gate electrode, and second diffusion layers of the first conductivity type, which have the same pattern shape as the first diffusion layers and are disposed spaced apart to sandwich the conductive layer, the second diffusion layers being electrically connected to the well.

摘要翻译： 半导体集成电路器件包括单元，每个单元包括设置在阱上的栅电极和设置在阱中的第二导电类型的第一扩散层，使得第一扩散层夹着栅电极， 第一扩散层用作源/排水管。 该器件还包括布置在逻辑电路结构区域的非占用区域中的子区域，每个子区域包括导体层，该导电层设置在阱上并具有与栅电极相同的图案形状 以及第一导电类型的第二扩散层，其具有与第一扩散层相同的图案形状并且间隔设置以夹持导电层，第二扩散层电连接到阱。

公开(公告)号：US20060082404A1

公开(公告)日：2006-04-20

申请号：US11245616

申请日：2005-10-07

申请人： Chihiro Ishii ,  Toshikazu Sei

发明人： Chihiro Ishii ,  Toshikazu Sei

IPC分类号： H03K3/356

CPC分类号： H03K3/0375 ,  H03K3/356156 ,  H03K3/356173

摘要： A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.

摘要翻译： 半导体集成电路包括第一数据保持部，第一上拉电路，第一下拉电路，第一反馈电路和第二反馈电路。 第一数据保持部保存第一输出数据。 第一个上拉电路将输入数据作为上拉控制信号，当上拉控制信号取一个值时，拉起第一个输出数据。 第一个下拉电路将输入数据作为下拉控制信号，当下拉控制信号取另一个值时，拉下第一个输出数据。 第一反馈电路将对应于第一输出数据的第一反馈信号作为上拉控制信号反馈到第一上拉电路。 第二反馈电路将与第一输出数据对应的第二反馈信号作为下拉控制信号反馈到第一下拉电路。