公开(公告)号：US07649581B2

公开(公告)日：2010-01-19

申请号：US11156476

申请日：2005-06-21

申请人： Young Seok Choi ,  Byung Yong Ahn ,  Hong Woo Yu ,  Ki Sul Cho

发明人： Young Seok Choi ,  Byung Yong Ahn ,  Hong Woo Yu ,  Ki Sul Cho

IPC分类号： G02F1/136

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136213 ,  G02F2001/13629

摘要： Disclosed is an array substrate of an LCD, and a method for fabricating it, which simplifies the fabrication process, thereby reducing fabrication costs. The process is simplified because the array substrate does not have a passivation film. The thin film transistors on the array substrate each have an active layer that is protected from contamination by forming a channel insulation layer on the active layer through a dry-etching process. Further, the gate line, gate pad, and gate electrode may have a two-layer structure having a low-resistance metal layer and a barrier metal layer, or a three-layer structure having a low-resistance metal layer and two barrier metal layers.

摘要翻译： 公开了一种LCD的阵列基板及其制造方法，其简化了制造工艺，从而降低了制造成本。 由于阵列基板不具有钝化膜，所以该过程被简化。 阵列基板上的薄膜晶体管每个都具有通过干蚀刻工艺在有源层上形成沟道绝缘层而防止污染的有源层。 此外，栅极线，栅极焊盘和栅电极可以具有具有低电阻金属层和阻挡金属层的双层结构，或者具有低电阻金属层和两个势垒金属层的三层结构 。

公开(公告)号：US07586123B2

公开(公告)日：2009-09-08

申请号：US11149689

申请日：2005-06-10

申请人： Young Seok Choi ,  Byung Yong Ahn ,  Ki Sul Cho ,  Hong Woo Yu

发明人： Young Seok Choi ,  Byung Yong Ahn ,  Ki Sul Cho ,  Hong Woo Yu

IPC分类号： H01L27/01

CPC分类号： H01L29/41733 ,  G02F1/136209 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1288

摘要： A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on-the semiconductor layer corresponding to the channel to protect the semiconductor layer.

摘要翻译： 公开了薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板保护薄膜晶体管而没有保护膜，从而降低制造成本。 在薄膜晶体管阵列基板中，栅电极连接到栅极线。 源电极连接到与栅极线交叉的数据线，以限定像素区域。 漏电极与源电极相对，其间具有沟道。 半导体层在通道中。 像素区域中的像素电极在两者之间的整个重叠区域上接触漏电极。 沟道保护膜设置在对应于沟道的半导体层上，以保护半导体层。

公开(公告)号：US20100001278A1

公开(公告)日：2010-01-07

申请号：US12541569

申请日：2009-08-14

申请人： Young Seok Choi ,  Byung Yong Ahn ,  Ki Sul Cho ,  Hong Woo Yu

发明人： Young Seok Choi ,  Byung Yong Ahn ,  Ki Sul Cho ,  Hong Woo Yu

IPC分类号： H01L33/00 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/41733 ,  G02F1/136209 ,  G02F2001/136236 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1288

摘要： A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on the semiconductor layer corresponding to the channel to protect the semiconductor layer.

摘要翻译： 公开了薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板保护薄膜晶体管而没有保护膜，从而降低制造成本。 在薄膜晶体管阵列基板中，栅电极连接到栅极线。 源电极连接到与栅极线交叉的数据线，以限定像素区域。 漏电极与源电极相对，其间具有沟道。 半导体层在通道中。 像素区域中的像素电极在两者之间的整个重叠区域上接触漏电极。 在对应于沟道的半导体层上提供沟道保护膜以保护半导体层。

公开(公告)号：US07589030B2

公开(公告)日：2009-09-15

申请号：US11476427

申请日：2006-06-27

申请人： Ki Sul Cho ,  Young Seok Choi ,  Byung Yong Ahn ,  Tae Ung Hwang ,  Dong Jun Min ,  Bo Kyoung Jung

发明人： Ki Sul Cho ,  Young Seok Choi ,  Byung Yong Ahn ,  Tae Ung Hwang ,  Dong Jun Min ,  Bo Kyoung Jung

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  Y10S438/95

摘要： A method of fabricating a liquid crystal display device includes performing a first mask process to form a gate line, a gate pad, and a gate electrode on a substrate. The method of fabricating a liquid crystal display device further includes performing a second mask process to form an active layer on the gate electrode, performing a third mask process to form a pixel electrode contacting the active layer, and performing a fourth mask process to form a source electrode and a drain electrode on the active layer.

摘要翻译： 制造液晶显示装置的方法包括：在基板上进行第一掩模处理以形成栅极线，栅极焊盘和栅电极。 制造液晶显示装置的方法还包括执行第二掩模处理以在栅电极上形成有源层，执行第三掩模处理以形成与活性层接触的像素电极，以及执行第四掩模处理以形成 源电极和有源层上的漏电极。

公开(公告)号：US09035312B2

公开(公告)日：2015-05-19

申请号：US11316895

申请日：2005-12-27

申请人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

发明人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

IPC分类号： H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  G02F1/1345 ,  G02F1/1362 ,  H01L27/12

CPC分类号： G02F1/13458 ,  G02F1/136213 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed therebetween; a semiconductor layer forming the channel between the source electrode and the drain electrode; a channel passivation layer formed on the channel to protect the semiconductor layer; a pixel electrode disposed in the pixel region to contact with the drain electrode; a storage capacitor including the pixel electrode extending over the gate line to form a storage area on a gate insulating layer on which a semiconductor layer pattern and a metal layer pattern are stacked; a gate pad extending from the gate line; and a data pad connected to the data line.

摘要翻译： 提供TFT阵列基板。 TFT阵列基板包括连接到栅极线的栅电极; 连接到数据线的源电极，所述数据线与所述栅极线交叉以限定像素区域; 面向源电极的漏电极，其间插入有沟道; 形成源电极和漏电极之间的沟道的半导体层; 形成在沟道上以保护半导体层的沟道钝化层; 设置在所述像素区域中以与所述漏电极接触的像素电极; 存储电容器，包括在所述栅极线上延伸的所述像素电极，以在其上层叠有半导体层图案和金属层图案的栅极绝缘层上形成存储区域; 从栅极线延伸的栅极焊盘; 以及连接到数据线的数据焊盘。

公开(公告)号：US08507301B2

公开(公告)日：2013-08-13

申请号：US12591657

申请日：2009-11-25

申请人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

发明人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

IPC分类号： H01L21/00

CPC分类号： H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/458

摘要： A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.

摘要翻译： TFT阵列基板包括：连接到栅极线的栅电极; 源极连接到与栅极线交叉以限定像素区域的数据线; 漏电极，其与源电极相对，沟道位于其间; 限定所述源电极和所述漏电极之间的沟道的半导体层; 像素区域中的像素电极并连接到漏电极; 在半导体层的沟道上的沟道钝化层; 从栅极线延伸的栅极焊盘，其中形成半导体图案和透明导电图案; 连接到数据线的数据焊盘，其中形成透明导电图案; 以及形成在半导体层下方的栅极绝缘层，栅极线和栅极焊盘，以及数据线和数据焊盘。

公开(公告)号：US07804089B2

公开(公告)日：2010-09-28

申请号：US11289506

申请日：2005-11-30

申请人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

发明人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

IPC分类号： H01L31/00

CPC分类号： G02F1/13458 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.

摘要翻译： 提供TFT阵列基板。 TFT阵列基板包括：栅极连接到栅极线; 源极连接到与栅极线交叉并限定像素区域的数据线; 面向源电极的漏电极，其间具有通道; 在源电极和漏电极之间形成沟道的半导体层; 像素区域中的像素电极并与漏电极接触; 形成在所述半导体层上的沟道钝化层; 栅极焊盘，其具有从栅极线延伸的栅极焊盘下部电极; 以及具有与数据线分离的数据焊盘下电极的数据焊盘。

公开(公告)号：US20100323482A1

公开(公告)日：2010-12-23

申请号：US12870395

申请日：2010-08-27

申请人： Young Seok CHOI ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

发明人： Young Seok CHOI ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

IPC分类号： H01L21/84

CPC分类号： G02F1/13458 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.

摘要翻译： 提供TFT阵列基板。 TFT阵列基板包括：栅极连接到栅极线; 源极连接到与栅极线交叉并限定像素区域的数据线; 面向源电极的漏电极，其间具有通道; 在源电极和漏电极之间形成沟道的半导体层; 像素区域中的像素电极并与漏电极接触; 形成在所述半导体层上的沟道钝化层; 栅极焊盘，其具有从栅极线延伸的栅极焊盘下部电极; 以及具有与数据线分离的数据焊盘下电极的数据焊盘。

公开(公告)号：US09018053B2

公开(公告)日：2015-04-28

申请号：US12870395

申请日：2010-08-27

申请人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

发明人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

IPC分类号： H01L21/00 ,  G02F1/1345 ,  H01L27/12 ,  G02F1/1362

CPC分类号： G02F1/13458 ,  G02F2001/136236 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288

摘要： A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.

摘要翻译： 提供TFT阵列基板。 TFT阵列基板包括：栅极连接到栅极线; 源极连接到与栅极线交叉并限定像素区域的数据线; 面向源电极的漏电极，其间具有通道; 在源电极和漏电极之间形成沟道的半导体层; 像素区域中的像素电极并与漏电极接触; 形成在所述半导体层上的沟道钝化层; 栅极焊盘，其具有从栅极线延伸的栅极焊盘下部电极; 以及具有与数据线分离的数据焊盘下电极的数据焊盘。

公开(公告)号：US20100075472A1

公开(公告)日：2010-03-25

申请号：US12591657

申请日：2009-11-25

申请人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

发明人： Young Seok Choi ,  Hong Woo Yu ,  Ki Sul Cho ,  Jae Ow Lee ,  Bo Kyoung Jung

IPC分类号： H01L21/336 ,  H01L21/02

CPC分类号： H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/458

摘要： A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.

摘要翻译： TFT阵列基板包括：连接到栅极线的栅电极; 源极连接到与栅极线交叉以限定像素区域的数据线; 漏电极，其与源电极相对，沟道位于其间; 限定所述源电极和所述漏电极之间的沟道的半导体层; 像素区域中的像素电极并连接到漏电极; 在半导体层的沟道上的沟道钝化层; 从栅极线延伸的栅极焊盘，其中形成半导体图案和透明导电图案; 连接到数据线的数据焊盘，其中形成透明导电图案; 以及形成在半导体层下方的栅极绝缘层，栅极线和栅极焊盘，以及数据线和数据焊盘。