公开(公告)号：US08008154B2

公开(公告)日：2011-08-30

申请号：US12188482

申请日：2008-08-08

申请人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

发明人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3145 ,  H01L21/31662

摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

摘要翻译： 形成绝缘膜的方法包括在基板上形成绝缘膜。 使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。 在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。 注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

公开(公告)号：US20090130834A1

公开(公告)日：2009-05-21

申请号：US12188482

申请日：2008-08-08

申请人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

发明人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

IPC分类号： H01L21/4763 ,  H01L21/469

CPC分类号： H01L29/42324 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3145 ,  H01L21/31662

摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

摘要翻译： 形成绝缘膜的方法包括在基板上形成绝缘膜。 使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。 在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。 注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

公开(公告)号：US20080085584A1

公开(公告)日：2008-04-10

申请号：US11857824

申请日：2007-09-19

申请人： Young-Jin Noh ,  Chul-Sung Kim ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Sung-Kweon Baek

发明人： Young-Jin Noh ,  Chul-Sung Kim ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Sung-Kweon Baek

IPC分类号： H01L21/336

CPC分类号： H01L21/28247 ,  H01L29/40114

摘要： Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure on a substrate, the gate structure including a control gate electrode, a blocking layer pattern, a floating gate electrode, and a tunnel insulating layer pattern. An oxidation process is performed that at least partially cures damage caused to the substrate and to the gate structure during formation of the gate structure. A first heat treatment is performed under a gas atmosphere including nitrogen to at least partially remove defect sites on the gate structure caused by the oxidation process. A second heat treatment is performed under a gas atmosphere including chlorine to at least partially remove remaining defect sites on the gate structure caused by the oxidation process.

摘要翻译： 公开了制造非易失性存储器件的方法，其可以至少部分地固化蚀刻损伤，并且可以至少部分地去除在器件的制造期间引起的器件的栅极结构中的缺陷位置。 制造非易失性存储器件的示例性方法包括在衬底上形成栅极结构，栅极结构包括控制栅电极，阻挡层图案，浮栅电极和隧道绝缘层图案。 进行氧化处理，其至少部分地固化在栅极结构形成期间对衬底和栅极结构的损伤。 在包括氮气的气体气氛下进行第一热处理，以至少部分地去除由氧化过程引起的栅极结构上的缺陷部位。 在包括氯的气体气氛下进行第二热处理，以至少部分地去除由氧化过程引起的栅极结构上的剩余缺陷部位。

公开(公告)号：US07799639B2

公开(公告)日：2010-09-21

申请号：US12123919

申请日：2008-05-20

申请人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

发明人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure.

摘要翻译： 非易失性存储器件的制造包括在半导体衬底上依次形成隧道氧化物层，第一导电层和氮化物层。 从隧道氧化物层，第一导电层和氮化物层形成堆叠图案，并且在与堆叠图案相邻的半导体衬底中形成沟槽。 执行氧化处理以在沟槽和第一导电层的侧壁上形成侧壁氧化物层。 将氯气引入经历氧化过程的堆叠图案的至少一部分中。 将Cl引入堆叠图案可以至少部分地固化在结构制造期间在其中引起的缺陷。

公开(公告)号：US20080299755A1

公开(公告)日：2008-12-04

申请号：US12123919

申请日：2008-05-20

申请人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

发明人： Young-jin Noh ,  Si-Young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Chul-sung Kim ,  Sung-kweon Baek

IPC分类号： H01L21/283

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure.

摘要翻译： 非易失性存储器件的制造包括在半导体衬底上依次形成隧道氧化物层，第一导电层和氮化物层。 从隧道氧化物层，第一导电层和氮化物层形成堆叠图案，并且在与堆叠图案相邻的半导体衬底中形成沟槽。 进行氧化处理以在沟槽和第一导电层的侧壁上形成侧壁氧化物层。 将氯气引入经历氧化过程的堆叠图案的至少一部分中。 将Cl引入堆叠图案可以至少部分地固化在结构制造期间在其中引起的缺陷。

公开(公告)号：US20090072294A1

公开(公告)日：2009-03-19

申请号：US11974636

申请日：2007-10-15

申请人： Sang-Ryol Yang ,  Sung-Kweon Baek ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang

发明人： Sang-Ryol Yang ,  Sung-Kweon Baek ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si3H8) gas as a silicon source gas. The tunnel oxide layer and the polysilicon layer are then patterned into a tunnel oxide layer pattern and a polysilicon layer pattern, respectively. A dielectric layer and a conductive layer corresponding to a control gate are subsequently formed on the polysilicon layer pattern. The polysilicon layer is formed using trisilane (Si3H8) gas as a result of which the polysilicon layer may be formed to have a relatively thin thickness while maintaining a thickness uniformity and realizing a superior morphology thus producing a floating gate having enhanced performance.

摘要翻译： 公开了一种使用相对薄的多晶硅层作为浮动栅极的非易失性存储器件的制造方法，其中在衬底上形成隧道氧化物层，然后形成厚度为约至大约的厚度的多晶硅层 使用丙硅烷（Si 3 H 8）气体作为硅源气体在隧道氧化物层上形成。 然后将隧道氧化物层和多晶硅层分别图案化为隧道氧化物层图案和多晶硅层图案。 随后在多晶硅层图案上形成对应于控制栅的电介质层和导电层。 使用丙硅烷（Si 3 H 8）气体形成多晶硅层，结果可以形成多晶硅层以具有相对较薄的厚度，同时保持厚度均匀性并实现优异的形态，从而产生具有增强性能的浮栅。

公开(公告)号：US20070034925A1

公开(公告)日：2007-02-15

申请号：US11586225

申请日：2006-10-25

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

IPC分类号： H01L29/94

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

摘要翻译： 提供了场效应晶体管（Fin-FET）。 翅片设置在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。 保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

公开(公告)号：US07535061B2

公开(公告)日：2009-05-19

申请号：US11586225

申请日：2006-10-25

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

IPC分类号： H01L21/84

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is provided on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is provided in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is provided on the first insulation layer and a second insulation layer is provided on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin.

摘要翻译： 提供了场效应晶体管（Fin-FET）。 翅片设置在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层设置在沟槽中，使得第一绝缘层的表面在鳍片的暴露翅片侧壁的表面下方凹进。 保护层设置在第一绝缘层上，第二绝缘层设置在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。

公开(公告)号：US07141456B2

公开(公告)日：2006-11-28

申请号：US10871742

申请日：2004-06-18

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  In-Soo Jung ,  Jin-Hwa Heo

IPC分类号： H01L21/84 ,  H01L21/332

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

摘要翻译： 提供制造鳍场效应晶体管（Fin-FET）的方法。 翅片形成在集成电路基板上。 翅片限定集成电路基板上的沟槽。 第一绝缘层形成在沟槽中，使得第一绝缘层的表面在鳍片的暴露在翅片的侧壁的表面下方凹进。 保护层形成在第一绝缘层上，并且第二绝缘层形成在沟槽中的保护层上，使得保护层位于第二绝缘层和鳍的侧壁之间。 还提供了相关的Fin-FET。

公开(公告)号：US08114735B2

公开(公告)日：2012-02-14

申请号：US11902209

申请日：2007-09-20

申请人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

发明人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yi

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/3185 ,  H01L29/4234 ,  H01L29/518 ,  H01L29/7923

摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

摘要翻译： 在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。 可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。 可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。 可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。 阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。 因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。