利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

109 条记录 (耗时 0.036 秒)

    OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES
    3.
    发明申请
    OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
    制造非易失性存储器件的氧化/热处理方法

    公开(公告)号：US20080085584A1

    公开(公告)日：2008-04-10

    申请号：US11857824

    申请日：2007-09-19

    申请人： Young-Jin Noh ,  Chul-Sung Kim ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Sung-Kweon Baek

    发明人： Young-Jin Noh ,  Chul-Sung Kim ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Sung-Kweon Baek

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28247 ,  H01L29/40114

    摘要： Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure on a substrate, the gate structure including a control gate electrode, a blocking layer pattern, a floating gate electrode, and a tunnel insulating layer pattern. An oxidation process is performed that at least partially cures damage caused to the substrate and to the gate structure during formation of the gate structure. A first heat treatment is performed under a gas atmosphere including nitrogen to at least partially remove defect sites on the gate structure caused by the oxidation process. A second heat treatment is performed under a gas atmosphere including chlorine to at least partially remove remaining defect sites on the gate structure caused by the oxidation process.

    摘要翻译： 公开了制造非易失性存储器件的方法，其可以至少部分地固化蚀刻损伤，并且可以至少部分地去除在器件的制造期间引起的器件的栅极结构中的缺陷位置。 制造非易失性存储器件的示例性方法包括在衬底上形成栅极结构，栅极结构包括控制栅电极，阻挡层图案，浮栅电极和隧道绝缘层图案。 进行氧化处理，其至少部分地固化在栅极结构形成期间对衬底和栅极结构的损伤。 在包括氮气的气体气氛下进行第一热处理，以至少部分地去除由氧化过程引起的栅极结构上的缺陷部位。 在包括氯的气体气氛下进行第二热处理，以至少部分地去除由氧化过程引起的栅极结构上的剩余缺陷部位。

    Method of manufacturing a non-volatile memory device
    4.
    发明申请
    Method of manufacturing a non-volatile memory device 审中-公开
    制造非易失性存储器件的方法

    公开(公告)号：US20090072294A1

    公开(公告)日：2009-03-19

    申请号：US11974636

    申请日：2007-10-15

    申请人： Sang-Ryol Yang ,  Sung-Kweon Baek ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang

    发明人： Sang-Ryol Yang ,  Sung-Kweon Baek ,  Si-Young Choi ,  Bon-Young Koo ,  Ki-Hyun Hwang

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si3H8) gas as a silicon source gas. The tunnel oxide layer and the polysilicon layer are then patterned into a tunnel oxide layer pattern and a polysilicon layer pattern, respectively. A dielectric layer and a conductive layer corresponding to a control gate are subsequently formed on the polysilicon layer pattern. The polysilicon layer is formed using trisilane (Si3H8) gas as a result of which the polysilicon layer may be formed to have a relatively thin thickness while maintaining a thickness uniformity and realizing a superior morphology thus producing a floating gate having enhanced performance.

    摘要翻译： 公开了一种使用相对薄的多晶硅层作为浮动栅极的非易失性存储器件的制造方法，其中在衬底上形成隧道氧化物层，然后形成厚度为约至大约的厚度的多晶硅层 使用丙硅烷（Si 3 H 8）气体作为硅源气体在隧道氧化物层上形成。 然后将隧道氧化物层和多晶硅层分别图案化为隧道氧化物层图案和多晶硅层图案。 随后在多晶硅层图案上形成对应于控制栅的电介质层和导电层。 使用丙硅烷（Si 3 H 8）气体形成多晶硅层，结果可以形成多晶硅层以具有相对较薄的厚度，同时保持厚度均匀性并实现优异的形态，从而产生具有增强性能的浮栅。

    Non-volatile semiconductor memory devices and methods of fabricating the same
    8.
    发明申请
    Non-volatile semiconductor memory devices and methods of fabricating the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20070063265A1

    公开(公告)日：2007-03-22

    申请号：US11601505

    申请日：2006-11-17

    申请人： Sung-Hae Lee ,  Chang-Hyun Lee ,  Ki-Hyun Hwang ,  Sung-Kweon Baek ,  Kwang-Min Park

    发明人： Sung-Hae Lee ,  Chang-Hyun Lee ,  Ki-Hyun Hwang ,  Sung-Kweon Baek ,  Kwang-Min Park

    IPC分类号： H01L29/788

    CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/513

    摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.

    摘要翻译： 公开了非易失性存储器件和制造非易失性存储器件的相关方法。 非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。 阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。 高电介质膜相对于电荷俘获层具有第一势垒。 阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。 阻挡绝缘膜的厚度在约5至约15的范围内。

    Non-volatile semiconductor memory devices and methods of fabricating the same
    9.
    发明授权
    Non-volatile semiconductor memory devices and methods of fabricating the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US07473959B2

    公开(公告)日：2009-01-06

    申请号：US11601505

    申请日：2006-11-17

    申请人： Sung-Hae Lee ,  Chang-Hyun Lee ,  Ki-Hyun Hwang ,  Sung-Kweon Baek ,  Kwang-Min Park

    发明人： Sung-Hae Lee ,  Chang-Hyun Lee ,  Ki-Hyun Hwang ,  Sung-Kweon Baek ,  Kwang-Min Park

    IPC分类号： H01L29/788

    CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/513

    摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.

    摘要翻译： 公开了非易失性存储器件和制造非易失性存储器件的相关方法。 非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。 阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。 高电介质膜相对于电荷俘获层具有第一势垒。 阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。 阻挡绝缘膜的厚度在约5至约15的范围内。

    Dram cell capacitors having U-shaped electrodes with rough inner and outer surfaces
    10.
    发明授权
    Dram cell capacitors having U-shaped electrodes with rough inner and outer surfaces 有权
    具有内表面和内表面粗糙的U形电极的电容器电容器

    公开(公告)号：US06838719B2

    公开(公告)日：2005-01-04

    申请号：US10223751

    申请日：2002-08-20

    申请人： Ki-Hyun Hwang ,  Chang-Won Choi ,  Seok-Woo Nam ,  Bon-Young Koo ,  Young-Sub Yu ,  Han-Jin Lim

    发明人： Ki-Hyun Hwang ,  Chang-Won Choi ,  Seok-Woo Nam ,  Bon-Young Koo ,  Young-Sub Yu ,  Han-Jin Lim

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/84

    摘要： Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode. This second electrically insulating layer preferably comprises a composite of a nitride layer and an oxide layer. To increase the effective surface area of the U-shaped electrode, an HSG layer may also be formed on the inner and outer sidewalls of the U-shaped electrode.