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    Semiconductor memory device including signal controller connected between memory blocks
    1.
    发明授权
    Semiconductor memory device including signal controller connected between memory blocks 有权
    半导体存储器件包括连接在存储块之间的信号控制器

    公开(公告)号：US08023346B2

    公开(公告)日：2011-09-20

    申请号：US12576284

    申请日：2009-10-09

    申请人： Young-hun Kim ,  Dong-hak Shin ,  Jin-seok Kwak

    发明人： Young-hun Kim ,  Dong-hak Shin ,  Jin-seok Kwak

    IPC分类号： G11C7/00

    CPC分类号： G11C29/81 ,  G11C8/14

    摘要： A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled.

    摘要翻译： 半导体存储器件包括第一存储器块，第二存储器块和信号控制器。 第一存储器块被配置为响应于行地址产生第一阻塞信号，第二阻塞信号和第一使能信号，并且响应于第一阻塞信号和第一阻塞信号而阻塞和使能存储器块的字线 使能信号。 第二存储器块被配置为响应于行地址产生第三阻塞信号，第四阻塞信号和第二使能信号，并且响应于第三阻塞信号和第二阻塞信号而阻止和使能第二存储器块的字线 第二使能信号。 信号控制器连接在第一存储器块和第二存储器块之间，并且被配置为当第二阻塞信号被使能时使能第三阻塞信号，并且当第四阻塞信号被使能时使能第一阻塞信号。

    Semiconductor memory devices having bit lines
    2.
    发明申请
    Semiconductor memory devices having bit lines 有权
    具有位线的半导体存储器件

    公开(公告)号：US20100128514A1

    公开(公告)日：2010-05-27

    申请号：US12591623

    申请日：2009-11-25

    申请人： Hyun-chul Yoon ,  Seong-jin Jang ,  Dong-hak Shin ,  Soo-hwan Kim ,  Hyuk-joon Kwon ,  Jong-min Oh

    发明人： Hyun-chul Yoon ,  Seong-jin Jang ,  Dong-hak Shin ,  Soo-hwan Kim ,  Hyuk-joon Kwon ,  Jong-min Oh

    IPC分类号： G11C7/06 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

    摘要： A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

    摘要翻译： 半导体器件包括连接到存储器块中的多个存储器单元的位线和具有连接到位线的第一节点的读出放大器和不连接到任何位线的第二节点。 第二节点的电容负载小于位线的容性负载。 感测放大器使用由电荷共享操作引起的第一节点和第二节点之间的电压差放大第一数据，以及使用第一节点和第二节点之间的电容性失配来放大第二数据。