公开(公告)号：US07339843B2

公开(公告)日：2008-03-04

申请号：US11229918

申请日：2005-09-19

申请人： Young-sun Min ,  Nam-jong Kim ,  Jong-hyun Choi

发明人： Young-sun Min ,  Nam-jong Kim ,  Jong-hyun Choi

IPC分类号： G11C29/00

CPC分类号： G11C29/82 ,  G11C17/18

摘要： A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.

摘要翻译： 可以通过生成与存储器件中的故障存储器位置的多个地址相对应的多个故障地址信号，然后将失败存储器位置的多个地址编程到故障存储器位置的多个地址来对 编程单元供读取或写入操作期间冗余电路用于故障存储单元的多个地址。

公开(公告)号：US20060062060A1

公开(公告)日：2006-03-23

申请号：US11229918

申请日：2005-09-19

申请人： Young-sun Min ,  Nam-jong Kim ,  Jong-hyun Choi

发明人： Young-sun Min ,  Nam-jong Kim ,  Jong-hyun Choi

IPC分类号： G11C29/00

CPC分类号： G11C29/82 ,  G11C17/18

摘要： A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.

摘要翻译： 可以通过生成与存储器件中的故障存储器位置的多个地址相对应的多个故障地址信号，然后将失败存储器位置的多个地址编程到故障存储器位置的多个地址来对 编程单元供读取或写入操作期间冗余电路用于故障存储单元的多个地址。

公开(公告)号：US07888770B2

公开(公告)日：2011-02-15

申请号：US11764385

申请日：2007-06-18

申请人： Kwang-kyu Bang ,  Jong-hyun Choi

发明人： Kwang-kyu Bang ,  Jong-hyun Choi

IPC分类号： H01L29/00

CPC分类号： H01L23/5258 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a second direction and having a second fuse pitch smaller than the first fuse pitch, and is arranged to bypass the first fuse or the second fuse.

摘要翻译： 公开了一种用于半导体器件的保险丝盒，并且包括：第一熔丝组，包括沿第一方向布置并具有第一切割轴的多个第一熔丝，每个第一熔丝包括具有第一熔丝间距的第一部分，第二部分 具有小于所述第一熔丝间距的第二熔丝节距和连接所述第一部分和所述第二部分的第三部分，包括沿所述第一方向布置并具有第二切割轴的多个第二熔丝的第二熔丝组，每个第二熔丝包括 具有第一熔丝间距的第一部分，具有小于第一熔丝间距的第二熔丝间距的第二部分和连接第一部分和第二部分的第三部分，以及包括多个第三熔丝的第三熔丝组，其中 每个第三保险丝具有第一切割轴或第二切割轴，包括沿第一方向布置并具有第一保险丝间距的第一图案，以及第二图案 rn布置在第二方向上并且具有小于第一熔丝间距的第二熔丝间距，并且被布置成绕过第一熔丝或第二熔丝。

公开(公告)号：US5959906A

公开(公告)日：1999-09-28

申请号：US977844

申请日：1997-11-25

申请人： Ho-sung Song ,  Jong-hyun Choi

发明人： Ho-sung Song ,  Jong-hyun Choi

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C11/407 ,  G11C29/00

CPC分类号： G11C29/808 ,  G11C29/785

摘要： A semiconductor memory device is shown that includes a normal memory cell array including a plurality of memory cells specified by 2.sup.n word lines and a plurality of column bit lines where an externally input n-bit row address is decoded to activate one of the 2.sup.n word lines. The semiconductor memory device further includes a redundant row fuse decoder that includes a plurality of n-bit address fuse portions each of which can be selectively coded to respond to an n-bit defective row address value in the externally input n-bit row address which corresponds to a word line in the normal memory cell array that includes a defective memory cell. The semiconductor memory device further includes a redundant memory cell array including a plurality of rows of memory cells which can be activated by one of the n-bit address fuse portions in response to the defective row address coded into the n-bit address fuse portion.

摘要翻译： 示出了包括正常存储单元阵列的半导体存储器件，其包括由2n个字线指定的多个存储器单元和多个列位线，其中外部输入的n位行地址被解码以激活2n个字线中的一个 。 半导体存储器件还包括冗余行熔丝解码器，其包括多个n位地址熔丝部分，每个n位地址熔丝部分可被选择性地编码以响应外部输入的n位行地址中的n位缺陷行地址值， 对应于包括有缺陷的存储器单元的正常存储单元阵列中的字线。 半导体存储器件还包括冗余存储单元阵列，该冗余存储单元阵列响应于被编码到n位地址熔丝部分中的缺陷行地址，可以由n位地址熔丝部分之一激活的多行存储单元。

公开(公告)号：US07177218B2

公开(公告)日：2007-02-13

申请号：US11117159

申请日：2005-04-28

申请人： Jong-hyun Choi ,  Beob-rae Cho ,  Young-hun Seo

发明人： Jong-hyun Choi ,  Beob-rae Cho ,  Young-hun Seo

IPC分类号： G11C7/04

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C2211/4061

摘要： A semiconductor device includes a DRAM and a temperature sense circuit. The DRAM has a refresh period that varies responsive to a temperature signal. The temperature sense circuit is configured to generate the temperature signal having a first binary value in response to sensing a temperature of the DRAM of at least a first temperature level, and to generate the temperature signal having a second binary value in response to sensing a temperature of the DRAM of less than a second temperature level, wherein the second temperature value is less than the first temperature value.

摘要翻译： 半导体器件包括DRAM和温度检测电路。 DRAM具有响应于温度信号而变化的刷新周期。 温度感测电路被配置为响应于感测至少第一温度水平的DRAM的温度而产生具有第一二进制值的温度信号，并且响应于感测温度而产生具有第二二进制值的温度信号 的DRAM，其中第二温度值小于第一温度值。

公开(公告)号：US20050276139A1

公开(公告)日：2005-12-15

申请号：US11117159

申请日：2005-04-28

申请人： Jong-hyun Choi ,  Beob-rae Cho ,  Young-hun Seo

发明人： Jong-hyun Choi ,  Beob-rae Cho ,  Young-hun Seo

IPC分类号： G11C7/04 ,  G11C11/406

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C2211/4061

摘要： A semiconductor device includes a DRAM and a temperature sense circuit. The DRAM has a refresh period that varies responsive to a temperature signal. The temperature sense circuit is configured to generate the temperature signal having a first binary value in response to sensing a temperature of the DRAM of at least a first temperature level, and to generate the temperature signal having a second binary value in response to sensing a temperature of the DRAM of less than a second temperature level, wherein the second temperature value is less than the first temperature value.

摘要翻译： 半导体器件包括DRAM和温度检测电路。 DRAM具有响应于温度信号而变化的刷新周期。 温度感测电路被配置为响应于感测至少第一温度水平的DRAM的温度而产生具有第一二进制值的温度信号，并且响应于感测温度而产生具有第二二进制值的温度信号 的DRAM，其中第二温度值小于第一温度值。

公开(公告)号：US07057446B2

公开(公告)日：2006-06-06

申请号：US10726095

申请日：2003-12-02

申请人： Jong-hyun Choi ,  Jae-hoon Kim ,  Jun-hyung Kim ,  Chi-wook Kim ,  Han-gu Sohn

发明人： Jong-hyun Choi ,  Jae-hoon Kim ,  Jun-hyung Kim ,  Chi-wook Kim ,  Han-gu Sohn

IPC分类号： G05F1/46 ,  G05F3/08

CPC分类号： G05F3/242

摘要： Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage generating circuit controls a reference voltage level according to an operating mode of the semiconductor memory device such that the operating characteristics of the semiconductor memory device can be improved in some operating modes and power dissipation can be minimized in other operating modes.

摘要翻译： 提供了用于控制内部电压电平的基准电压发生电路和内部电压产生电路，其中基准电压发生电路包括分配单元，钳位控制单元和控制单元; 分配单元响应于外部电源电压具有低于外部电源电压的电压电平，并且经由输出端子输出根据操作模式而变化的参考电压; 所述钳位控制单元连接在所述输出端子和接地电压之间，并且响应于具有低于所述参考电压的电压电平的控制电压，将所述参考电压的电压电平钳位在恒定电平; 控制单元响应于第一和第二操作模式信号而增加或减小参考电压的电压电平; 所述控制单元包括第一控制晶体管和第二控制晶体管; 并且参考电压产生电路根据半导体存储器件的操作模式控制参考电压电平，使得可以在一些操作模式下改善半导体存储器件的工作特性，并且在其它操作模式中可以使功率损耗最小化。

公开(公告)号：US06560158B2

公开(公告)日：2003-05-06

申请号：US09981782

申请日：2001-10-17

申请人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

发明人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

IPC分类号： G11C800

CPC分类号： G11C5/143

摘要： A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.

公开(公告)号：US06535440B2

公开(公告)日：2003-03-18

申请号：US09906896

申请日：2001-07-16

申请人： Kyu-Nam Lim ,  Jong-hyun Choi ,  Sang-suk Kang

发明人： Kyu-Nam Lim ,  Jong-hyun Choi ,  Sang-suk Kang

IPC分类号： G11C700

CPC分类号： G11C29/56 ,  G01R31/319

摘要： An apparatus and a method are disclosed for package level burn-in test circuit in semiconductor devices. The apparatus includes a package burn-in register, a test voltage generator for the package level burn-in test, a burn-in master signal generator, and a burn-in test circuit. The package burn-in register stores a package burn-in set-order from the outside and generates a package burn-in set-signal. The test voltage generator generates burn-in test voltages in response to the package burn-in set-signal and to address signals through first address terminals from the outside. The burn-in master signal generator generates a burn-in master signal by combining and receiving the second address signal form first address terminals, a wafer burn-in enable signal from a control signal input terminal, and the package burn-in set-signal. After receiving the burn-in master signal, multiple address signals from multiple third address terminals, and the test voltages for the package level burn-in test, the burn-in test circuit performs a package level burn-in test.

公开(公告)号：US06381188B1

公开(公告)日：2002-04-30

申请号：US09481251

申请日：2000-01-11

申请人： Jong-hyun Choi ,  Dong-il Seo ,  Jong-sik Na

发明人： Jong-hyun Choi ,  Dong-il Seo ,  Jong-sik Na

IPC分类号： G11C700

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622

摘要： A dynamic random access memory (DRAM) including a plurality of memory banks is capable of selectively performing a self-refresh operation with respect to only a subset of the banks. The DRAM includes a plurality of row decoders for selecting word lines of the memory cells of the memory banks, an address generator for generating internal addresses which sequentially vary during a self-refresh mode, a refresh bank designating circuit for generating refresh bank designating signals for designating a memory bank to be refreshed, and a bank selection decoder for designating one or more memory banks to be refreshed by the refresh bank designating signals and supplying refresh addresses to the row decoders corresponding to the designated memory banks according to the information of the internal addresses. The self-refresh operation is performed for only selected memory banks, or alternatively, only in those memory banks in which data is stored, thereby minimizing power consumption.

摘要翻译： 包括多个存储体的动态随机存取存储器（DRAM）能够仅针对存储体的子集选择性地进行自刷新操作。 DRAM包括用于选择存储体的存储单元的字线的多个行解码器，用于产生在自刷新模式期间顺序变化的内部地址的地址发生器，用于产生刷新存储区指定信号的刷新存储体指定电路， 指定要刷新的存储体，以及存储体选择解码器，用于指定要由刷新存储体指定信号刷新的一个或多个存储体，并根据内部信息向与指定存储体相对应的行解码器提供刷新地址 地址 仅对所选择的存储体执行自刷新操作，或者仅在存储数据的那些存储体中执行自刷新操作，从而最小化功耗。