公开(公告)号：US07599234B2

公开(公告)日：2009-10-06

申请号：US11349995

申请日：2006-02-09

申请人： Jeong-Sik Nam ,  Ho-Sung Song

发明人： Jeong-Sik Nam ,  Ho-Sung Song

IPC分类号： G11C11/063

CPC分类号： G11C5/063 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

摘要： A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

摘要翻译： 半导体存储器件可以具有存储单元阵列，其中相应的存储单元设置在行和列的相交处。 半导体存储器件还可以包括至少一个解码器和至少一个延迟控制器。 解码器可以选择存储器单元的行或列。 信号延迟控制器可以基于与所选择的行或列相关联的至少一个存储器单元的位置和行负载中的至少一个来控​​制由至少一个解码器施加到行或列的激活信号的延迟 所选存储单元的电容值。

公开(公告)号：US06310796B1

公开(公告)日：2001-10-30

申请号：US09631062

申请日：2000-08-01

申请人： Ho-Sung Song

发明人： Ho-Sung Song

IPC分类号： G11C506

CPC分类号： G11C7/1084 ,  G11C7/1078 ,  G11C11/4096

摘要： A dynamic random access memory device and a &mgr;BGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n data input pads, and x reference voltage pads. Each input receiver operates synchronously with a clock signal and includes a differential amplifying unit that generates an output data signal according to a voltage difference between an input data signal and a reference voltage. The n data input pads respectively connect to the n input receivers and transfer the input data signals to the input receivers. The n input receivers are divided into x groups according to their positions, and the x reference voltage input pads respectively connect to the x groups of input receivers for commonly applying the reference voltage to the input receivers in the respective groups. Each reference voltage input pad can connect to its group of input receivers through one or multiple common lines. The package includes a first ball that receives the reference voltage. The first ball is commonly connected to the x reference voltage input pads of the device. The average and maximum distances between the reference voltage input pads and input receivers are much shorter with multiple reference voltage pads. Accordingly, the noise level of the reference voltage is smaller, thereby improving a margin in data setup and hold times of the input receivers and the operational reliability of products. Filters connected to the reference voltage pads can further reduce the noise in the reference voltage at the input receivers.

摘要翻译： 动态随机存取存储器件和器件的muBGA封装使用多个焊盘作为参考电压。 该器件包括n个输入接收器，n个数据输入焊盘和x个参考电压焊盘。 每个输入接收器与时钟信号同步工作，并且包括差分放大单元，其根据输入数据信号和参考电压之间的电压差产生输出数据信号。 n个数据输入焊盘分别连接到n个输入接收器，并将输入数据信号传送到输入接收器。 n个输入接收器根据它们的位置被分成x组，并且x参考电压输入焊盘分别连接到x组输入接收器，以通常将参考电压施加到相应组中的输入接收器。 每个参考电压输入板可以通过一条或多条公共线连接到其组输入接收器。 该包装包括接收参考电压的第一球。 第一个球通常连接到设备的x参考电压输入焊盘。 多个参考电压焊盘，参考电压输入焊盘和输入接收器之间的平均和最大距离要短得多。 因此，参考电压的噪声电平较小，从而提高了输入接收机的数据建立和保持时间以及产品的操作可靠性。 连接到参考电压焊盘的滤波器可以进一步降低输入接收器处参考电压的噪声。

公开(公告)号：US06178109B1

公开(公告)日：2001-01-23

申请号：US09457511

申请日：1999-12-08

申请人： Ho-sung Song ,  Jei-hwan Yoo

发明人： Ho-sung Song ,  Jei-hwan Yoo

IPC分类号： G11C1300

CPC分类号： G11C7/222 ,  G11C7/1078

摘要： Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

摘要翻译： 集成电路存储器件包括具有参考电压输入端的一个或多个输入接收器。 导体将参考电压输入端子电耦合到参考电压，并且电容器连接在导体和第一接地电压之间。 优选地，根据输入接收器的电特性来选择电容器和导体之间的连接的位置。 因此，电容器可以减小施加到输入接收器的参考电压输入端的参考电压中的波动或噪声。 参考电压中的波动或噪声可能导致输入接收器的输入特性和/或设置和保持时间相对于彼此变化。 参考电压的波动或噪声的降低可能导致输入接收器之间的输入特性更一致，并且在设置和保持时间内更加一致。

公开(公告)号：US08027219B2

公开(公告)日：2011-09-27

申请号：US12585636

申请日：2009-09-21

申请人： Jeong-Sik Nam ,  Ho-Sung Song

发明人： Jeong-Sik Nam ,  Ho-Sung Song

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08

摘要： A semiconductor memory device may have a memory cell array with respective memory cells disposed at intersections of rows and columns. The semiconductor memory device may also include at least one decoder and at least one delay controller. The decoder may select a row or column of the memory cell. The signal delay controller may control a delay of an activation signal applied to the row or column by the at least one decoder based on at least one of a position of the at least one memory cell associated with the selected row or column and a line loading capacitance value of the selected memory cell.

摘要翻译： 半导体存储器件可以具有存储单元阵列，其中相应的存储单元设置在行和列的相交处。 半导体存储器件还可以包括至少一个解码器和至少一个延迟控制器。 解码器可以选择存储器单元的行或列。 信号延迟控制器可以基于与所选择的行或列相关联的至少一个存储器单元的位置和行负载中的至少一个来控​​制由至少一个解码器施加到行或列的激活信号的延迟 所选存储单元的电容值。

公开(公告)号：US06366155B1

公开(公告)日：2002-04-02

申请号：US09613367

申请日：2000-07-10

申请人： Byung-sick Moon ,  Mi-seon Kang ,  Ho-sung Song

发明人： Byung-sick Moon ,  Mi-seon Kang ,  Ho-sung Song

IPC分类号： G05F110

CPC分类号： H03K5/1534

摘要： Reference voltage regulators and methods for integrated circuit output driver systems generate an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to an output enable signal. Preferably, sufficient initial supplementary current is generated to compensate for an initial drop in the reference voltage that is generated by a reference voltage generator upon initial activation of the output driver system. Reference voltage generators according to embodiments of the invention may be included in an integrated circuit output driver system that is responsive to a reference voltage and to an output enable signal, and that varies in current drive capability in response to a current drive control signal. These embodiments of reference voltage regulators include a reference voltage generator that generates the reference voltage for the integrated circuit output driver system. A supplementary current generator generates an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to the output enable signal. In some embodiments, the supplementary current generator generates a fixed initial supplementary current for the integrated circuit output driver system. In other embodiments, the supplementary current generator generates a variable initial supplementary current for the integrated circuit output driver system at the reference voltage for the predetermined time period in response to the output enable signal, and that varies in response to the current drive control signal.

摘要翻译： 用于集成电路输出驱动器系统的参考电压调节器和方法响应于输出使能信号在预定时间周期内以参考电压产生集成电路输出驱动器系统的初始辅助电流。 优选地，产生足够的初始辅助电流以补偿在初始激活输出驱动器系统时由参考电压发生器产生的参考电压的初始下降。 根据本发明的实施例的参考电压发生器可以包括在响应于参考电压和输出使能信号的集成电路输出驱动器系统中，并且响应于当前驱动控制信号而在电流驱动能力中变化。 参考电压调节器的这些实施例包括产生用于集成电路输出驱动器系统的参考电压的参考电压发生器。 辅助电流发生器响应于输出使能信号，在预定时间周期内以参考电压产生用于集成电路输出驱动器系统的初始辅助电流。 在一些实施例中，辅助电流发生器为集成电路输出驱动器系统产生固定的初始辅助电流。 在其他实施例中，辅助电流发生器响应于输出使能信号而在预定时间段内以参考电压产生用于集成电路输出驱动器系统的可变初始辅助电流，并且响应于当前驱动控制信号而变化。

公开(公告)号：US6115311A

公开(公告)日：2000-09-05

申请号：US979

申请日：1997-12-30

申请人： Ho-Sung Song ,  Jong-Hyun Choi ,  Jun-Young Jyun

发明人： Ho-Sung Song ,  Jong-Hyun Choi ,  Jun-Young Jyun

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1045

摘要： A semiconductor memory device having an improved column select control circuit. The semiconductor memory device includes a memory cell array consisting of a plurality of volatile memory cells and a column select line decoder for selecting a column line of the memory cell array. The semiconductor memory device includes at least two different refresh cycle modes designed within a single chip. A mode select circuit generates a mode select signal for selecting one of at least two refresh modes. A column select control circuit controls the enable time of the column select line decoder enable signal responsive to the mode select signal and to row address strobe signal for providing the column select line decoder enable signal to the column select line decoder.

摘要翻译： 一种具有改进的列选择控制电路的半导体存储器件。 半导体存储器件包括由多个易失性存储器单元组成的存储单元阵列和用于选择存储单元阵列的列线的列选择线解码器。 半导体存储器件包括在单个芯片内设计的至少两种不同的刷新周期模式。 模式选择电路产生用于选择至少两种刷新模式之一的模式选择信号。 列选择控制电路响应于模式选择信号控制列选择线解码器使能信号的使能时间和行地址选通信号，以向列选择行解码器提供列选择线解码器使能信号。

公开(公告)号：US20060028900A1

公开(公告)日：2006-02-09

申请号：US11197227

申请日：2005-08-04

申请人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

发明人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

IPC分类号： G11C8/00 ,  G11C7/06 ,  G11C29/00

CPC分类号： G11C7/18 ,  G11C29/808 ,  G11C29/846

摘要： A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

摘要翻译： 存储器件具有至少一对存储单元块，备用行解码器，数据交换控制信号发生器和数据交换单元。 当第一存储器单元块中的有缺陷的存储器单元用邻近（或相邻）第一存储器单元块的第二存储器单元块中的备用存储器单元修复时，第一存储器单元的存储单元的数据拓扑可以 与第二存储单元块的存储单元匹配。

公开(公告)号：US06239642B1

公开(公告)日：2001-05-29

申请号：US09437897

申请日：1999-11-09

申请人： Jong-sun Kim ,  Sung-min Hwang ,  Ho-sung Song

发明人： Jong-sun Kim ,  Sung-min Hwang ,  Ho-sung Song

IPC分类号： H03H1126

CPC分类号： G08C19/10

摘要： A variable loading circuit for controlling signal transmission on a signal line in an integrated circuit includes a capacitor. A loading control circuit is responsive to a control signal to variably couple the signal line and a signal node through the capacitor and thereby vary signal transmission time on the signal line. In embodiments of the present invention, the loading control circuit includes a series combination of a fuse and one or more switches. The one or more switches are responsive to respective control signals to variably couple the signal line to the signal node through the fuse and the capacitor. The variable loading circuits can be used to reduce skew among signals in systems where signal timing is critical. Related methods are also described.

摘要翻译： 用于控制集成电路中的信号线上的信号传输的可变负载电路包括电容器。 负载控制电路响应控制信号，以通过电容器可变地耦合信号线和信号节点，从而改变信号线上的信号传输时间。 在本发明的实施例中，加载控制电路包括熔丝和一个或多个开关的串联组合。 一个或多个开关响应于相应的控制信号，以通过熔丝和电容器将信号线可变地耦合到信号节点。 可变负载电路可用于减少信号时序至关重要的系统中的信号之间的偏差。 还描述了相关方法。

公开(公告)号：US07319634B2

公开(公告)日：2008-01-15

申请号：US11501905

申请日：2006-08-08

申请人： Chul-Hwan Choo ,  Ho-Sung Song

发明人： Chul-Hwan Choo ,  Ho-Sung Song

IPC分类号： G11C8/00

CPC分类号： G11C8/18 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4082 ,  G11C29/18

摘要： An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

摘要翻译： 半导体器件的地址转换器包括时钟产生部分，用于在施加电源电压时产生至少一个时钟信号; 控制信号设定装置，用于在模式设定操作期间设定控制信号; 极性选择信号产生部分，用于响应于至少一个时钟信号和控制信号产生至少一个极性选择信号; 以及地址转换部分，用于转换从外部部分施加的地址的至少一位，以响应于所述至少一个极性选择信号输出转换的地址。

公开(公告)号：US20070153619A1

公开(公告)日：2007-07-05

申请号：US11501905

申请日：2006-08-08

申请人： Chul-Hwan Choo ,  Ho-Sung Song

发明人： Chul-Hwan Choo ,  Ho-Sung Song

IPC分类号： G11C8/00

CPC分类号： G11C8/18 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4082 ,  G11C29/18

摘要： An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

摘要翻译： 半导体器件的地址转换器包括时钟产生部分，用于在施加电源电压时产生至少一个时钟信号; 控制信号设定装置，用于在模式设定操作期间设定控制信号; 极性选择信号产生部分，用于响应于至少一个时钟信号和控制信号产生至少一个极性选择信号; 以及地址转换部分，用于转换从外部部分施加的地址的至少一位，以响应于所述至少一个极性选择信号输出转换的地址。