公开(公告)号：US06510096B2

公开(公告)日：2003-01-21

申请号：US09981945

申请日：2001-10-17

申请人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

发明人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

IPC分类号： G11C802

CPC分类号： G11C5/143 ,  G11C7/22

摘要： A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

公开(公告)号：US06560158B2

公开(公告)日：2003-05-06

申请号：US09981782

申请日：2001-10-17

申请人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

发明人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

IPC分类号： G11C800

CPC分类号： G11C5/143

摘要： A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.

公开(公告)号：US5751642A

公开(公告)日：1998-05-12

申请号：US702356

申请日：1996-08-23

申请人： Jei-hwan Yoo

发明人： Jei-hwan Yoo

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096 ,  G11C7/1048

摘要： A voltage control circuit is used to control the voltage levels on input and output lines of a semiconductor memory device. A load transistor is controlled by feeding back an output voltage of the input and output lines in order to increase data access speed. The input and output lines are separately controlled by clamp devices that clamp low voltage levels on the input and output lines to voltages between a ground potential and a power supply voltage. The clamping devices are enabled during read operations by feeding back the output data from a sense amplifier coupled to the input and output lines. The sense amplifier senses and amplifies the voltage difference of the input and output lines. The feedback control signal from the sense amplifier eliminates DC current paths while the voltage of the input and output lines are toggled between high and low states. The voltage control circuit increases operation speed and reduces current consumption in the memory device.

摘要翻译： 电压控制电路用于控制半导体存储器件的输入和输出线上的电压电平。 通过反馈输入和输出线的输出电压来控制负载晶体管，以便增加数据访问速度。 输入和输出线由钳位装置分别控制，钳位装置将输入和输出线路上的低电压电平钳位到地电位和电源电压之间的电压。 通过从耦合到输入和输出线路的读出放大器反馈输出数据，读取操作期间钳位装置被使能。 读出放大器感测并放大输入和输出线的电压差。 来自读出放大器的反馈控制信号消除了直流电流路径，同时输入和输出线的电压在高和低态之间切换。 电压控制电路提高了操作速度并降低了存储器件中的电流消耗。

公开(公告)号：US06178109B1

公开(公告)日：2001-01-23

申请号：US09457511

申请日：1999-12-08

申请人： Ho-sung Song ,  Jei-hwan Yoo

发明人： Ho-sung Song ,  Jei-hwan Yoo

IPC分类号： G11C1300

CPC分类号： G11C7/222 ,  G11C7/1078

摘要： Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

摘要翻译： 集成电路存储器件包括具有参考电压输入端的一个或多个输入接收器。 导体将参考电压输入端子电耦合到参考电压，并且电容器连接在导体和第一接地电压之间。 优选地，根据输入接收器的电特性来选择电容器和导体之间的连接的位置。 因此，电容器可以减小施加到输入接收器的参考电压输入端的参考电压中的波动或噪声。 参考电压中的波动或噪声可能导致输入接收器的输入特性和/或设置和保持时间相对于彼此变化。 参考电压的波动或噪声的降低可能导致输入接收器之间的输入特性更一致，并且在设置和保持时间内更加一致。

公开(公告)号：US6151264A

公开(公告)日：2000-11-21

申请号：US280026

申请日：1999-03-26

申请人： Jei-hwan Yoo

发明人： Jei-hwan Yoo

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/413 ,  G11C8/00

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222

摘要： Integrated circuit memory devices include first and second spaced-apart memory banks in an integrated circuit substrate. A pad block in the integrated circuit substrate is located between the first and second spaced-apart memory banks. An input/output block in the integrated circuit substrate is connected to the pad block to receive input data from external of the integrated circuit memory device via the pad block and to transmit output data to external of the integrated circuit memory device via the pad block. A delay locked loop in the integrated circuit substrate is responsive to an external clock signal to generate an internal clock signal. An interface logic block in the integrated circuit substrate is responsive to the internal clock signal to control the first and second memory banks and the input/output block in response to the internal clock signal. A single data shift block in the integrated circuit substrate is located between the pad block and one of the first and second spaced-apart memory banks. The single data shift block is connected to the input/output block by a first plurality of lines and to both of the first and second memory banks by a second plurality of lines that is an integer multiple of the first plurality. The single data shift block converts serial data on the first plurality of lines to parallel data on the second plurality of lines and converts parallel data on the second plurality of lines to serial data on the first plurality of lines. The invention may be used in any integrated circuit memory device. However, the invention is preferably used in a packet type integrated circuit memory device that operates on packets of data address and control signals, such as a Rambus integrated circuit memory device.

摘要翻译： 集成电路存储器件包括集成电路衬底中的第一和第二间隔开的存储体。 集成电路基板中的焊盘块位于第一和第二间隔开的存储体之间。 集成电路衬底中的输入/输出块连接到焊盘块，以经由焊盘块从集成电路存储器件的外部接收输入数据，并经由焊盘块将输出数据发送到集成电路存储器件的外部。 集成电路衬底中的延迟锁定环路响应外部时钟信号以产生内部时钟信号。 集成电路衬底中的接口逻辑块响应于内部时钟信号响应于内部时钟信号来控制第一和第二存储器组和输入/输出块。 集成电路基板中的单个数据移位块位于焊盘块和第一和第二间隔开的存储体之一之间。 单个数据移位块通过第一多个线路连接到输入/输出块，并且通过作为第一多个行的整数倍的第二多个线路连接到第一和第二存储体两者。 单个数据移位块将第一多个行上的串行数据转换成第二个多行的并行数据，并将第二个多个行上的并行数据转换为第一个多行的串行数据。 本发明可以用于任何集成电路存储器件中。 然而，本发明优选地用于对诸如Rambus集成电路存储器件的数据地址和控制信号的分组进行操作的分组型集成电路存储器件。

公开(公告)号：US06335897B1

公开(公告)日：2002-01-01

申请号：US09608017

申请日：2000-06-30

申请人： Jei-hwan Yoo

发明人： Jei-hwan Yoo

IPC分类号： G11C800

CPC分类号： G11C29/787 ,  G11C29/808

摘要： A semiconductor memory device including a redundancy circuit having latch cells is provided. In the semiconductor memory device, memory cells are selected in memory cell blocks each having a plurality of memory cells arrayed in columns and rows. Data of the selected memory cells is input to or output from the memory cell blocks via data lines. The semiconductor memory device includes a row decoder, a sub word line driver, latch cells, fuse boxes, a latch cell control unit, and a switch unit. The row decoder decodes a row address and generates a word line enable signal for selecting the word lines of a group of memory cells among memory cells. The sub word line driver is connected to the word line enable signal, and drives the selected memory cells. The latch cells are arranged along the data lines. Each of the fuse boxes has a plurality of fuses which are programmed in accordance with a defective cell address in the memory cell block. The latch cell control unit generates a latch cell selection signal in response to the output signal of each of the fuse boxes, and selects latch cells. The switch units connect the selected latch cells to the data lines in response to the latch cell selection signal.

摘要翻译： 提供了包括具有锁存单元的冗余电路的半导体存储器件。 在半导体存储器件中，在存储单元块中选择存储单元，每个存储单元块具有以行和列排列的多个存储单元。 所选择的存储单元的数据经由数据线被输入到存储单元块或从存储单元块输出。 半导体存储器件包括行解码器，子字线驱动器，锁存单元，保险丝盒，锁存单元控制单元和开关单元。 行解码器对行地址进行解码，并生成用于选择存储单元中的一组存储单元的字线的字线使能信号。 子字线驱动器连接到字线使能信号，并驱动选定的存储单元。 锁存单元沿数据线布置。 每个保险丝盒具有多个保险丝，其根据存储器单元块中的有缺陷的单元地址进行编程。 锁存单元控制单元响应于每个保险丝盒的输出信号产生锁存单元选择信号，并选择锁存单元。 开关单元响应于锁存单元选择信号将所选择的锁存单元连接到数据线。

公开(公告)号：US06252808B1

公开(公告)日：2001-06-26

申请号：US09001712

申请日：1997-12-31

申请人： Jei-hwan Yoo

发明人： Jei-hwan Yoo

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/84

摘要： A semiconductor memory device having a row redundancy scheme in which the time to enable a word line during a normal path is less than that of a conventional device, to enhance the operation speed of a memory chip, and the number of common redundancies are maximized to enhance the redundancy capability, and a method for curing a defective cell. The semiconductor memory device has a plurality of global blocks, each of which includes a plurality of unit matrixes having a normal block and a redundancy block, a normal division word line driver, a redundancy division word line driver, a main decoder and an auxiliary decoder. In the main decoder, an output signal is selectively activated according to a row address signal regardless of using the redundancy cell. Also, in the auxiliary decoder, when a corresponding global block is selected according to the row address signal for selecting a global block in a normal operation mode or a redundancy scheme of the corresponding block is used in the redundancy operation mode, an output signal is selectively activated according to the row address signal.

摘要翻译： 具有行冗余方案的半导体存储器件，其中在正常路径期间使字线的时间小于常规器件的时间，以增强存储器芯片的操作速度，并且将普通冗余的数量最大化为 增强冗余能力，以及固化缺陷单元的方法。 半导体存储器件具有多个全局块，每个块包括具有正常块和冗余块的多个单位矩阵，正常分割字线驱动器，冗余分割字线驱动器，主解码器和辅助解码器 。 在主解码器中，无论使用冗余单元如何，根据行地址信号选择性地激活输出信号。 此外，在辅助解码器中，当根据用于在正常操作模式中选择全局块的行地址信号选择对应的全局块时，或者在冗余操作模式中使用相应块的冗余方案时，输出信号为 根据行地址信号选择性地激活。

公开(公告)号：US6064601A

公开(公告)日：2000-05-16

申请号：US104475

申请日：1998-06-25

申请人： Jei-hwan Yoo ,  Byung-chul Kim

发明人： Jei-hwan Yoo ,  Byung-chul Kim

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/32 ,  G11C29/34 ,  G11C16/04

CPC分类号： G11C29/32

摘要： Integrated circuit memory devices can reduce write time during a write cycle of a parallel bit test mode. The memory devices include a simultaneous column select line activation circuit that simultaneously activates at least two of the plurality of column select lines during a write cycle of a parallel bit test mode. Therefore, during the write cycle, at least two bit lines are simultaneously connected to one input and output line since at least two column select lines are simultaneously activated by the simultaneous column select line activation circuit. Accordingly, data is simultaneously written to the memory cells connected to at least two bit lines through the input and output line.

摘要翻译： 集成电路存储器件可以在并行位测试模式的写周期期间减少写入时间。 存储器件包括同时列选择线激活电路，其在并行位测试模式的写周期期间同时激活多个列选择线中的至少两个。 因此，在写入周期期间，至少两条位线同时连接到一条输入和输出线，因为至少两条列选择线同时被同时列选择线激活电路激活。 因此，通过输入和输出线将数据同时写入连接到至少两个位线的存储单元。

公开(公告)号：US5940343A

公开(公告)日：1999-08-17

申请号：US924465

申请日：1997-08-21

申请人： Gi-won Cha ,  Jei-hwan Yoo ,  Hoon Choi

发明人： Gi-won Cha ,  Jei-hwan Yoo ,  Hoon Choi

IPC分类号： G11C11/41 ,  G11C8/08 ,  G11C11/40 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C8/08

摘要： A semiconductor memory device includes a sub-wordline and a bit line connected to a memory cell, a sub-wordline driver for signaling the sub-wordline, and a main word decoder and a sub-word decoder, for selecting the sub-wordline driver in response to an external input address signal, wherein the wordline driver includes an NMOS transistor switch connected between a main wordline which is an output of the main word decoder and the sub-wordline, and wherein the logic "high" voltage level of a first control signal which controls the switch is lower than that of a signal output to the sub-wordline. The semiconductor memory device having the sub-wordline driver allows the internal power supply voltage to be used as the power supply voltage of the main word decoder. Accordingly, the reliability of a gate oxide film of a transistor constituting the main word decoder is improved, which lengthens the life of the semiconductor memory device.

摘要翻译： 一种半导体存储器件包括一个子字线和连接到存储单元的位线，一个用于发出子字线信号的子字线驱动器，以及一个主字解码器和一个子字解码器，用于选择子字线驱动器 响应于外部输入地址信号，其中所述字线驱动器包括连接在作为所述主字解码器的输出的主字线和所述子字线之间的NMOS晶体管开关，并且其中所述逻辑“高”电压电平为第一 控制开关的控制信号低于输出到子字线的信号的控制信号。 具有子字线驱动器的半导体存储器件允许内部电源电压用作主字解码器的电源电压。 因此，提高构成主字解码器的晶体管的栅极氧化膜的可靠性，这延长了半导体存储器件的寿命。

公开(公告)号：US5907514A

公开(公告)日：1999-05-25

申请号：US58053

申请日：1998-04-09

申请人： Jae-woong Lee ,  Jei-hwan Yoo

发明人： Jae-woong Lee ,  Jei-hwan Yoo

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  G11C29/06

CPC分类号： G11C29/24 ,  G11C29/06 ,  G11C29/785 ,  G11C29/802

摘要： A circuit and method are shown for controlling a redundant memory cell of an integrated memory circuit. The circuit includes a decoder, a precharge enable unit, a redundant controller, a redundant enable signal generator, and a redundant memory cell array. The precharge enable unit is connected to the decoder, and responds to a precharge enable signal by precharging the output terminal of decoder. The decoder responds to a first row address signal by discharging the output terminal of the decoder unless the value of the row address signal corresponds to a programmed address of the decoder. The redundant enable signal generator samples the voltage level of the output terminal of the decoder under control of a redundant control signal of the redundant controller in order to generate a redundant cell enable signal. The redundant controller generates the redundant control signal in response to a second row address signal, where the redundant controller delays the redundant control signal by a predetermined time interval in response to a stress test signal which is active during a stress test in order to allow the decoder sufficient time to discharge the output terminal during the stress test. The redundant memory cell array is connected to the redundant enable signal generator and responds to the redundant enable signal.

摘要翻译： 示出了用于控制集成存储器电路的冗余存储单元的电路和方法。 电路包括解码器，预充电使能单元，冗余控制器，冗余使能信号发生器和冗余存储单元阵列。 预充电使能单元连接到解码器，并且通过对解码器的输出端进行预充电来响应预充电使能信号。 解码器通过对解码器的输出端进行放电来响应第一行地址信号，除非行地址信号的值对应于解码器的编程地址。 冗余使能信号发生器在冗余控制器的冗余控制信号的控制下对解码器的输出端子的电压电平进行采样，以产生冗余单元使能信号。 冗余控制器响应于第二行地址信号产生冗余控制信号，其中响应于在应力测试期间有效的应力测试信号，冗余控制器将冗余控制信号延迟预定时间间隔，以便允许 解码器在压力测试期间有足够的时间来排出输出端子。 冗余存储单元阵列连接到冗余使能信号发生器并响应冗余使能信号。