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公开(公告)号：US07109748B1
公开(公告)日：2006-09-19
申请号：US11147759
申请日：2005-06-07
申请人： Yow-Juang W Liu , Hugh Sungki O , Richard G Cliff
发明人： Yow-Juang W Liu , Hugh Sungki O , Richard G Cliff
IPC分类号： H03K19/173
CPC分类号： H03K19/0016
摘要： Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned off using a reverse bias voltage rather than a ground voltage. A charge pump circuit on the integrated circuit may be used to generate the reverse bias voltage. The reverse bias voltage may also be provided from an external source. The integrated circuit may be a programmable logic device in which logic is configured by providing programming data to configuration cells. The configuration cells may be used to apply either a positive power supply voltage to a given transistor to turn that transistor on or to provide the reverse bias voltage to that transistor to turn that transistor off.
摘要翻译： 可以使用降低晶体管漏电流的反向偏置晶体管控制装置来降低集成电路待机功耗。 集成电路晶体管可以使用反向偏置电压而不是接地电压来关断。 可以使用集成电路上的电荷泵电路来产生反向偏置电压。 也可以从外部源提供反向偏置电压。 集成电路可以是可编程逻辑器件，其中通过向配置单元提供编程数据来配置逻辑。 配置单元可以用于将正电源电压施加到给定晶体管以将该晶体管导通，或者向该晶体管提供反向偏置电压以将该晶体管截止。
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公开(公告)号：US07981753B1
公开(公告)日：2011-07-19
申请号：US12683402
申请日：2010-01-06
IPC分类号： H01L21/331
CPC分类号： H01L27/0266 , H01L21/265 , H01L29/0692 , H01L29/41775 , H01L29/456 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
摘要翻译： 提供了一种用于提供静电放电（ESD）保护的装置。 该器件包括其中形成有漏极，源极和栅极的半导体衬底。 漏极包含具有比漏极和源极的其余部分的电阻高的电阻的区域。 栅极区域与该较高电阻区域和源极接触。 在一个实施例中，为了提供更高的电阻，较高的电阻缺少硅化物。 包括形成用于提供ESD保护的装置的方法。
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3.发明授权公开(公告)号：US07286020B1
公开(公告)日：2007-10-23
申请号：US11231641
申请日：2005-09-21
IPC分类号： G01R31/00 , G01R23/00 , H03K19/003 , G06F11/16
CPC分类号： H03K19/00315 , H03K19/00369
摘要： Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first periodic signal to the frequency of a second periodic signal. The difference in the frequency between the first periodic signal and the second periodic signal indirectly indicates how much the threshold voltages of the transistors have shifted. The difference in frequency between the two periodic signals can be monitored to determine the speed and performance of circuits on the chip. The output of the frequency detector can also indicate when to replace low performing circuits with higher performing circuits. When the frequency of the second periodic signal differs from the frequency of the first periodic signal by a predefined percentage, a low performing circuit is replaced with a higher performing replica circuit.
摘要翻译： 提供技术用于监视电路的性能，并用更高性能的电路代替低性能电路。 频率检测器将第一周期信号的频率与第二周期信号的频率进行比较。 第一周期信号和第二周期信号之间的频率差异间接地指示晶体管的阈值电压已经偏移了多少。 可以监视两个周期信号之间的频率差，以确定芯片上电路的速度和性能。 频率检测器的输出也可以指示什么时候更换具有较高性能电路的低性能电路。 当第二周期信号的频率与预定百分比的第一周期信号的频率不同时，低执行电路被更高性能的复制电路代替。
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公开(公告)号：US07671416B1
公开(公告)日：2010-03-02
申请号：US10956758
申请日：2004-09-30
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L21/265 , H01L29/0692 , H01L29/41775 , H01L29/456 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
摘要翻译： 提供了一种用于提供静电放电（ESD）保护的装置。 该器件包括其中形成有漏极，源极和栅极的半导体衬底。 漏极包含具有比漏极和源极的其余部分的电阻高的电阻的区域。 栅极区域与该较高电阻区域和源极接触。 在一个实施例中，为了提供更高的电阻，较高的电阻缺少硅化物。 包括形成用于提供ESD保护的装置的方法。
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公开(公告)号：US07279952B1
公开(公告)日：2007-10-09
申请号：US11223270
申请日：2005-09-09
IPC分类号： H03K5/08
CPC分类号： H03K5/08 , H03K19/018507
摘要： A voltage converter includes a first N-channel MOSFET transistor, an inverter, a plurality of serially-connected diodes and a second N-channel MOSFET transistor. The inverter is coupled to the gate of the first N-channel MOSFET transistor to turn on/off the voltage converter. The anode of the diodes is coupled to the source of the first N-channel MOSFET transistor and the cathode of the diodes are coupled to the drain of the second N-channel MOSFET transistor. Since the source of the second N-channel MOSFET transistor is ground, the voltage clamped at the source of the first N-channel MOSFET transistor is not higher than 3.4V when a high voltage applied to the gate of the second N-channel MOSFET transistor turns it on.
摘要翻译： 电压转换器包括第一N沟道MOSFET晶体管，反相器，多个串联二极管和第二N沟道MOSFET晶体管。 反相器耦合到第一N沟道MOSFET晶体管的栅极以导通/关断电压转换器。 二极管的阳极耦合到第一N沟道MOSFET晶体管的源极，二极管的阴极耦合到第二N沟道MOSFET晶体管的漏极。 由于第二N沟道MOSFET晶体管的源极被接地，所以当施加到第二N沟道MOSFET晶体管的栅极的高电压时，钳位在第一N沟道MOSFET晶体管的源极处的电压不高于3.4V 打开它。
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6.发明授权公开(公告)号：US07511533B1
公开(公告)日：2009-03-31
申请号：US11364779
申请日：2006-02-27
IPC分类号： H03K19/0175
CPC分类号： H03K19/01721
摘要： Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.
摘要翻译： 具有用于较高输出电流驱动的寄生晶体管的输出装置的电路，方法和装置。 一个这样的MOS输出装置包括辅助输出电压转换的寄生双极晶体管。 寄生晶体管可以是MOS器件的结构中固有的。 或者，可以将一个或多个区域（例如注入或扩散区域）添加到MOS器件中以形成或增强寄生双极器件。 寄生晶体管在适当的输出转换期间导通，一旦转换完成，该寄生晶体管就会断开。 寄生器件可以通过将电流注入下拉器件的体积中，通过将电流从上拉器件的主体中拉出，或者通过将输出器件的大部分绑定到适当的电压，例如 用于下拉器件的VCC或用于上拉器件的接地。
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公开(公告)号：US07170810B1
公开(公告)日：2007-01-30
申请号：US11153987
申请日：2005-06-16
摘要： Voltage regulator circuitry is provided that produces a stable programming-voltage on a programmable integrated circuit. The programmable integrated circuit has programming control circuitry that provides logic-level programming signals. A controllable voltage supply increases the strength of the logic-level programming signals to produce programming-voltage-level programming signals. The programming-voltage-level programming signals are used to program programmable elements such as flash transistors on the programmable integrated circuit. A temperature-insensitive diode-based voltage feedback circuit is connected to the output of the controllable voltage supply. The voltage feedback circuit provides a corresponding feedback voltage to the controllable voltage supply that the controllable voltage supply used to stabilize the magnitude of the programming-voltage-level programming signals.
摘要翻译： 提供了电压调节器电路，在可编程集成电路上产生稳定的编程电压。 可编程集成电路具有提供逻辑电平编程信号的编程控制电路。 可控电压电源增加了逻辑电平编程信号的强度，以产生编程电压电平编程信号。 编程电压电平编程信号用于对可编程集成电路上的闪存晶体管等可编程元件进行编程。 基于温度敏感的二极管电压反馈电路连接到可控电压源的输出端。 电压反馈电路向可控电压源提供相应的反馈电压，可控电压电源用于稳定编程电压电平编程信号的幅度。
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公开(公告)号：US07638847B1
公开(公告)日：2009-12-29
申请号：US11339907
申请日：2006-01-25
IPC分类号： H01L23/62 , H01L29/72 , H01L29/74 , H01L31/111 , H01L29/73
CPC分类号： H01L27/0259
摘要： An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.
摘要翻译： ESD保护结构部分地包括在衬底中的阱中的源极和漏极以及衬底上的栅极的NMOS晶体管，源极和漏极连接在地和串联二极管之间，栅极连接到地 。 该结构还包括具有连接到输入焊盘的阴极和连接到阱的阳极的二极管，使得在输入焊盘上的正电压ESD事件的情况下二极管被反向偏置。 结果，在正电压ESD事件中，雪崩效应快速地将电流注入到衬底中并因此注入到寄生双极晶体管的基极中，以便触发晶体管导通并放电ESD脉冲。 或者，二极管是齐纳二极管，电流由齐纳二极管的效应产生。 互补结构提供了针对负ESD脉冲的保护。
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公开(公告)号：US07342282B2
公开(公告)日：2008-03-11
申请号：US10938102
申请日：2004-09-10
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/74
摘要： A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated with a first doping type, and the second semiconductor region is associated with a second doping type different from the first doping type. The second semiconductor region is located directly on an insulating layer.
摘要翻译： 一种用于静电放电保护的半导体器件和方法。 半导体器件包括第一半导体可控整流器和第二半导体可控整流器。 第一半导体可控整流器包括第一半导体区域和第二半导体区域，并且第二半导体可控整流器包括第一半导体区域和第二半导体区域。 第一半导体区域与第一掺杂型相关联，并且第二半导体区域与不同于第一掺杂型的第二掺杂型相关联。 第二半导体区域直接位于绝缘层上。
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公开(公告)号：US07333312B2
公开(公告)日：2008-02-19
申请号：US11173254
申请日：2005-07-01
IPC分类号： H02H9/00
CPC分类号： H01L27/0285
摘要： An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.
摘要翻译： ESD器件发明包括形成在衬底中的第一和第二晶体管，每个具有源极，漏极和栅极，第一事务的源极和漏极连接在地和I / O引脚或输入之间， 第一晶体管连接到地，并且第二晶体管的源极和漏极连接在第一晶体管的衬底和I / O引脚或输入之间; 在地和I / O引脚或输入之间串联连接的第一和第二电容器; 以及至少第三晶体管，其连接在第一和第二电容器之间的接地和节点之间，第二晶体管的栅极也连接到该节点。
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