摘要:
A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned on/off by the constant voltage applied from the voltage control unit; and a second switching unit that is connected to the input stage and is turned on/off by a signal applied from the input stage.
摘要:
Provided is a device for generating a chaotic signal comprising a PN signal generator that is composed of a digital logic circuit and generates a digital pseudo random signal with a predetermined frequency; a voltage control that generates a clock signal with a predetermined frequency; a mixer that mixes the pseudo random signal and the clock signal so as to generate a chaotic signal to output; and a band-pass filter that filters the chaotic signal, output from the mixer, into a chaotic signal of a desired band and then outputs the filtered signal.
摘要:
A current mode logic (CML)-CMOS converter comprises an input stage that is turned on/off by receiving an input voltage from the outside; a voltage control unit that outputs a constant voltage; a first switching unit that is connected to the input stage and the voltage control unit and is turned on/off by the constant voltage applied from the voltage control unit; and a second switching unit that is connected to the input stage and is turned on/off by a signal applied from the input stage.
摘要:
Provided is a dual-system transmitting device comprising a chaos signal generator that generates a chaos signal; a band-pass filter that filters the generated chaos signal into a signal within an information transmission bandwidth preset in a transmission side; an impulse signal generator that generates an impulse signal synchronized with a transmitted signal; a switching element that selectively outputs the chaos signal passing through the band-pass filter and the generated impulse signal; an amplifier that amplifies the signal selected by the switching element; and a signal transmitting unit that transmits the signal amplified by the amplifier through an antenna. When the signal amplified by the amplifier is a chaos signal, the signal transmitting unit modulates the amplified signal through an OOK (on-off keying) scheme such that the signal is transmitted as a carrier of a transmitted signal. When the signal amplified by the amplifier is an impulse signal, the signal transmitting unit passes the signal to transmit.Provided is a dual-system receiving device, which is applied to both a received signal using a chaos signal as a carrier and a received signal using an impulse signal as a carrier, the dual-system receiving device comprising a band-pass filter that filters a received signal into a signal within an information transmission bandwidth preset in a reception side; an amplifier that amplifies the filtered received signal; a first demodulator that, when the amplified received signal is a received signal using a chaos signal as a carrier, demodulates the amplified received signal; a second demodulator that, when the amplified received signal is a received signal using an impulse signal as a carrier, demodulates the amplified received signal; and a switching element that selectively outputs the received signal amplified by the amplifier to the first or second demodulator.
摘要:
Provided is a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an EM simulation. The method includes the steps of: (a) extracting the design specifications of the RFIC so as design and simulate a circuit; (b) designing the layout of the designed and simulated circuit, and extracting layout parameters by using the designed layout; (c) simplifying the layout and carrying out the EM simulation to extract performance parameters; (d) carrying out a circuit simulation by using the extracted layout parameters and performance parameters, and judging whether the results of the circuit simulation satisfy the design specifications of the RFIC or not; (e) when it is judged that the results of the circuit simulation satisfy the design specifications of the RFIC, performing a circuit manufacturing process; and (f) when it is not judged that the results of the circuit simulation satisfy the design specifications of the RFIC, partially removing the layout, and carrying out the EM simulation, thereby analyzing and compensating a performance degradation region.
摘要:
There is provided an ultra-wide band pulse signal generator that can vary a waveform and bandwidth of a pulse signal by delaying transmitted data according to a clock signal without using a delay line to generate the pulse signal. An ultra-wide band pulse signal generator according to an aspect of the invention may include: a signal generating unit sequentially delaying transmitted data according to a predetermined clock signal to generate a plurality of pulse signals; an amplification unit amplifying the plurality of pulse signals from the signal generating unit according to predetermined amplification ratios; and a combination unit combining the plurality of pulse signals amplified by the amplification unit.
摘要:
Provided is a method for compensating performance degradation of a radio frequency integrated circuit (RFIC) using an EM simulation. The method includes the steps of: (a) extracting the design specifications of the RFIC so as design and simulate a circuit; (b) designing the layout of the designed and simulated circuit, and extracting layout parameters by using the designed layout; (c) simplifying the layout and carrying out the EM simulation to extract performance parameters; (d) carrying out a circuit simulation by using the extracted layout parameters and performance parameters, and judging whether the results of the circuit simulation satisfy the design specifications of the RFIC or not; (e) when it is judged that the results of the circuit simulation satisfy the design specifications of the RFIC, performing a circuit manufacturing process; and (f) when it is not judged that the results of the circuit simulation satisfy the design specifications of the RFIC, partially removing the layout, and carrying out the EM simulation, thereby analyzing and compensating a performance degradation region.
摘要:
In a DC offset cancellation circuit, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor connected between the inverse terminal and the output terminal. A DC offset cancellation resistor is connected between the inverse terminal and the non-inverse terminal. Also, in each of first and second DC offset cancellation circuits of the programmable gain amplifier, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor is connected between the inverse terminal and the output terminal. A DC offset cancellation circuit is connected between the inverse terminal and the non-inverse terminal. Here, the first and second DC offset cancellation circuits are connected with each other in series.
摘要:
A location awareness system using RFID and a wireless communication apparatus for the location awareness are provided. The location awareness system includes a RFID tag, a wireless communication apparatus for location awareness, more than three anchors, a coordinator, and a server. The wireless communication apparatus identifies the target object with the RFID attached through communicating with the RFID tag. The anchors receive information about the identified target object and measuring a distance by communication with the wireless communication apparatus using a predetermined wireless communication scheme. The coordinator collects the measure distance and the information from each of the anchors. The server calculates a location of the target object by receiving information about the measured distances and the target objects from the coordinator and calculating the location of the wireless communication apparatus using the received information.
摘要:
In a DC offset cancellation circuit, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor connected between the inverse terminal and the output terminal. A DC offset cancellation resistor is connected between the inverse terminal and the non-inverse terminal. Also, in each of first and second DC offset cancellation circuits of the programmable gain amplifier, an operational amplifier is provided with an inverse terminal, a non-inverse terminal and an output terminal. A first resistor is connected to the non-inverse terminal. A second resistor is connected between the inverse terminal and the output terminal. A DC offset cancellation circuit is connected between the inverse terminal and the non-inverse terminal. Here, the first and second DC offset cancellation circuits are connected with each other in series.