公开(公告)号：US07521741B2

公开(公告)日：2009-04-21

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US20080001189A1

公开(公告)日：2008-01-03

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US20070267693A1

公开(公告)日：2007-11-22

申请号：US11419685

申请日：2006-05-22

申请人： Hsing-Yi Chien ,  Yu-Chang Jong ,  Ruey-Hsin Liu ,  Te-Yin Hsia

发明人： Hsing-Yi Chien ,  Yu-Chang Jong ,  Ruey-Hsin Liu ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/7816

摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.

摘要翻译： 半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。

公开(公告)号：US08004038B2

公开(公告)日：2011-08-23

申请号：US11419685

申请日：2006-05-22

申请人： Hsing-Yi Chien ,  Yu-Chang Jong ,  Te-Yin Hsia ,  Ruey-Shin Liu

发明人： Hsing-Yi Chien ,  Yu-Chang Jong ,  Te-Yin Hsia ,  Ruey-Shin Liu

IPC分类号： H01L31/062

CPC分类号： H01L29/7835 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/7816

摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.

摘要翻译： 半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。