公开(公告)号：US08435824B2

公开(公告)日：2013-05-07

申请号：US13177686

申请日：2011-07-07

申请人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Jen-Cheng Liu ,  Wen-De Wang ,  Yueh-Chiou Lin

发明人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Jen-Cheng Liu ,  Wen-De Wang ,  Yueh-Chiou Lin

IPC分类号： H01L21/00 ,  H01L31/00

CPC分类号： H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2224/0345 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure comprises a device substrate having a front side and a back side; an interconnect structure disposed on the front side of the device substrate; and a bonding pad connected to the interconnect structure. The bonding pad comprises a recessed region in a dielectric material layer; a dielectric mesa of the dielectric material layer interposed between the recessed region; and a metal layer disposed in the recessed region and on the dielectric mesa.

摘要翻译： 本公开提供了半导体结构的一个实施例。 半导体结构包括具有正面和背面的器件基板; 布置在所述器件基板的前侧的互连结构; 以及连接到互连结构的接合焊盘。 焊盘包括电介质材料层中的凹陷区域; 插入在凹陷区域之间的电介质材料层的电介质台面; 以及设置在凹陷区域和电介质台面上的金属层。

公开(公告)号：US08987855B2

公开(公告)日：2015-03-24

申请号：US13198057

申请日：2011-08-04

申请人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

发明人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

IPC分类号： H01L27/146 ,  H01L31/18 ,  H01L31/02

CPC分类号： H01L27/14687 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464

摘要： An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening.

公开(公告)号：US08664736B2

公开(公告)日：2014-03-04

申请号：US13112755

申请日：2011-05-20

申请人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Wen-De Wang ,  Yueh-Chiou Lin

发明人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Wen-De Wang ,  Yueh-Chiou Lin

IPC分类号： H01L27/146

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a device substrate having a front side and a back side. The semiconductor device further includes an interconnect structure disposed on the front side of the device substrate, the interconnect structure having a n-number of metal layers. The semiconductor device also includes a bonding pad disposed on the back side of the device substrate, the bonding pad extending through the interconnect structure and directly contacting the nth metal layer of the n-number of metal layers.

摘要翻译： 一种半导体器件，包括具有正面和背面的器件基板。 半导体器件还包括设置在器件基板的前侧的互连结构，该互连结构具有n个金属层。 半导体器件还包括设置在器件衬底的背面上的接合焊盘，焊盘延伸穿过互连结构并直接接触n个金属层的第n个金属层。

公开(公告)号：US20130032916A1

公开(公告)日：2013-02-07

申请号：US13198111

申请日：2011-08-04

申请人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

发明人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

IPC分类号： H01L31/0224

CPC分类号： H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14685 ,  H01L27/14689 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/11916 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/83359 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

摘要翻译： 集成电路结构包括半导体衬底和从半导体衬底的底表面延伸到半导体衬底中的介质衬垫。 低k电介质层设置在半导体衬底下方。 第一个非低k电介质层位于低k电介质层的下面。 金属焊盘位于第一非低k电介质层的下面。 第二个非低k电介质层位于金属焊盘的下方。 开口从半导体衬底的顶表面向下延伸以穿透半导体衬底，电介质衬垫和低k电介质层，其中，开口焊接在金属衬垫的顶表面上。 钝化层包括在开口的侧壁上的部分，其中去除开口底部的钝化层的一部分。

公开(公告)号：US20130009270A1

公开(公告)日：2013-01-10

申请号：US13177686

申请日：2011-07-07

申请人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Jen-Cheng Liu ,  Wen-De Wang ,  Yueh-Chiou Lin

发明人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Jen-Cheng Liu ,  Wen-De Wang ,  Yueh-Chiou Lin

IPC分类号： H01L31/0224 ,  H01L31/18 ,  H01L23/485

CPC分类号： H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2224/0345 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure comprises a device substrate having a front side and a back side; an interconnect structure disposed on the front side of the device substrate; and a bonding pad connected to the interconnect structure. The bonding pad comprises a recessed region in a dielectric material layer; a dielectric mesa of the dielectric material layer interposed between the recessed region; and a metal layer disposed in the recessed region and on the dielectric mesa.

摘要翻译： 本公开提供了半导体结构的一个实施例。 半导体结构包括具有正面和背面的器件基板; 布置在所述器件基板的前侧的互连结构; 以及连接到互连结构的接合焊盘。 焊盘包括电介质材料层中的凹陷区域; 插入在凹陷区域之间的电介质材料层的电介质台面; 以及设置在凹陷区域和电介质台面上的金属层。

公开(公告)号：US09013022B2

公开(公告)日：2015-04-21

申请号：US13198111

申请日：2011-08-04

申请人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

发明人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

IPC分类号： H01L31/00 ,  H01L23/00 ,  H01L23/48 ,  H01L27/146 ,  H01L21/768 ,  H01L23/525

CPC分类号： H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L27/14623 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14685 ,  H01L27/14689 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/11916 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/83359 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

摘要翻译： 集成电路结构包括半导体衬底和从半导体衬底的底表面延伸到半导体衬底中的介质衬垫。 低k电介质层设置在半导体衬底下方。 第一个非低k电介质层位于低k电介质层的下面。 金属焊盘位于第一非低k电介质层的下面。 第二个非低k电介质层位于金属焊盘的下方。 开口从半导体衬底的顶表面向下延伸以穿透半导体衬底，电介质衬垫和低k电介质层，其中，开口焊接在金属衬垫的顶表面上。 钝化层包括在开口的侧壁上的部分，其中去除开口底部的钝化层的一部分。

公开(公告)号：US20130032920A1

公开(公告)日：2013-02-07

申请号：US13198057

申请日：2011-08-04

申请人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

发明人： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-De Wang ,  Shuang-Ji Tsai ,  Yueh-Chiou Lin

IPC分类号： H01L27/146 ,  H01L31/18 ,  H01L31/02

CPC分类号： H01L27/14687 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464

摘要： An image sensor device includes a semiconductor substrate having a front side and a backside. A first dielectric layer is on the front side of the semiconductor substrate. A metal pad is in the first dielectric layer. A second dielectric layer is over the first dielectric layer and on the front side of the semiconductor substrate. An opening penetrates through the semiconductor substrate from the backside of the semiconductor substrate, wherein the opening includes a first portion extending to expose a portion of the metal pad and a second portion extending to expose a portion of the second dielectric layer. A metal layer is formed in the first portion and the second portion of the opening.

公开(公告)号：US20120292730A1

公开(公告)日：2012-11-22

申请号：US13112755

申请日：2011-05-20

申请人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Wen-De Wang ,  Yueh-Chiou Lin

发明人： Shuang-Ji Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Wen-De Wang ,  Yueh-Chiou Lin

IPC分类号： H01L27/146 ,  H01L31/18 ,  H01L31/0224

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a device substrate having a front side and a back side. The semiconductor device further includes an interconnect structure disposed on the front side of the device substrate, the interconnect structure having a n-number of metal layers. The semiconductor device also includes a bonding pad disposed on the back side of the device substrate, the bonding pad extending through the interconnect structure and directly contacting the nth metal layer of the n-number of metal layers.

摘要翻译： 一种半导体器件，包括具有正面和背面的器件基板。 半导体器件还包括设置在器件基板的前侧的互连结构，该互连结构具有n个金属层。 半导体器件还包括设置在器件衬底的背面上的接合焊盘，焊盘延伸穿过互连结构并直接接触n个金属层的第n个金属层。

公开(公告)号：US07521741B2

公开(公告)日：2009-04-21

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US20080001189A1

公开(公告)日：2008-01-03

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。