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公开(公告)号：US09105570B2
公开(公告)日：2015-08-11
申请号：US13548783
申请日：2012-07-13
申请人： Yu-Chen Su , Huang-Ming Chen , Chun-Feng Nieh , Pei-Chao Su
发明人： Yu-Chen Su , Huang-Ming Chen , Chun-Feng Nieh , Pei-Chao Su
IPC分类号： H01L21/00 , H01L21/26 , H01L21/225 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0638 , H01L21/225 , H01L21/26586 , H01L21/31155 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76834 , H01L21/76897 , H01L27/092 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/66606 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.
摘要翻译： 一个实施方案是一种方法，其包括通过基底的表面扩散碳，通过基底的表面注入碳，以及在扩散碳并将碳注入到基底的表面之后退火基底。 衬底包括第一栅极，栅极间隔物，蚀刻停止层和层间电介质。 第一个栅极在半导体衬底之上。 栅极间隔物沿着第一栅极的侧壁。 蚀刻停止层位于栅极间隔物的表面上并在半导体衬底的表面上方。 层间电介质在蚀刻停止层之上。 衬底的表面包括层间电介质的表面。
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2.发明申请Methods for Introducing Carbon to a Semiconductor Structure and Structures Formed Thereby 有权将碳引入到由此形成的半导体结构和结构的方法公开(公告)号：US20140015104A1
公开(公告)日：2014-01-16
申请号：US13548783
申请日：2012-07-13
申请人： Yu-Chen Su , Huang-Ming Chen , Chun-Feng Nieh , Pei-Chao Su
发明人： Yu-Chen Su , Huang-Ming Chen , Chun-Feng Nieh , Pei-Chao Su
IPC分类号： H01L21/38 , H01L29/772
CPC分类号： H01L29/0638 , H01L21/225 , H01L21/26586 , H01L21/31155 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76834 , H01L21/76897 , H01L27/092 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/66606 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.
摘要翻译： 一个实施方案是一种方法，其包括通过基底的表面扩散碳，通过基底的表面注入碳，以及在扩散碳并将碳注入到基底的表面之后退火基底。 衬底包括第一栅极，栅极间隔物，蚀刻停止层和层间电介质。 第一个栅极在半导体衬底之上。 栅极间隔物沿着第一栅极的侧壁。 蚀刻停止层位于栅极间隔物的表面上并在半导体衬底的表面上方。 层间电介质在蚀刻停止层之上。 衬底的表面包括层间电介质的表面。
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公开(公告)号：US20100270627A1
公开(公告)日：2010-10-28
申请号：US12428011
申请日：2009-04-22
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.
摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括提供基板; 在所述衬底上形成至少一个栅极结构; 在所述衬底中形成多个掺杂区域; 在衬底上形成蚀刻停止层; 去除所述蚀刻停止层的第一部分，其中所述蚀刻停止层的第二部分保留在所述多个掺杂区域上; 在衬底上形成硬掩模层; 去除所述硬掩模层的第一部分，其中所述硬掩模层的第二部分保留在所述至少一个栅极结构上; 以及通过所述硬掩模层的所述第二部分形成到所述至少一个栅极结构的第一接触，以及通过所述蚀刻停止层的所述第二部分到所述多个掺杂区域的第二接触。
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公开(公告)号：US20120228679A1
公开(公告)日：2012-09-13
申请号：US13475245
申请日：2012-05-18
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.
摘要翻译： 公开了在接触形成期间保护栅极结构的各种方法。 一种示例性方法包括：在衬底上形成栅极结构，其中栅极结构包括栅极，栅极结构插入设置在衬底中的源极区域和漏极区域; 图案化第一蚀刻停止层，使得第一蚀刻停止层设置在源极区域和漏极区域上; 图案化第二蚀刻停止层，使得第二蚀刻停止层设置在栅极结构上; 以及形成源极接触，漏极接触和栅极接触，其中所述源极接触和所述漏极接触延伸穿过所述第一蚀刻停止层，并且所述栅极接触延伸穿过所述第二蚀刻停止层，其中形成所述源极接触， 漏极接触，并且栅极接触包括同时移除第一蚀刻停止层和第二蚀刻停止层以暴露栅极，源极区域和漏极区域。
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公开(公告)号：US08497169B2
公开(公告)日：2013-07-30
申请号：US13475245
申请日：2012-05-18
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.
摘要翻译： 公开了在接触形成期间保护栅极结构的各种方法。 一种示例性方法包括：在衬底上形成栅极结构，其中栅极结构包括栅极，栅极结构插入设置在衬底中的源极区域和漏极区域; 图案化第一蚀刻停止层，使得第一蚀刻停止层设置在源极区域和漏极区域上; 图案化第二蚀刻停止层，使得第二蚀刻停止层设置在栅极结构上; 以及形成源极接触，漏极接触和栅极接触，其中所述源极接触和所述漏极接触延伸穿过所述第一蚀刻停止层，并且所述栅极接触延伸穿过所述第二蚀刻停止层，其中形成所述源极接触， 漏极接触，并且栅极接触包括同时移除第一蚀刻停止层和第二蚀刻停止层以暴露栅极，源极区域和漏极区域。
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公开(公告)号：US08202776B2
公开(公告)日：2012-06-19
申请号：US12428011
申请日：2009-04-22
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.
摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括提供基板; 在所述衬底上形成至少一个栅极结构; 在所述衬底中形成多个掺杂区域; 在衬底上形成蚀刻停止层; 去除所述蚀刻停止层的第一部分，其中所述蚀刻停止层的第二部分保留在所述多个掺杂区域上; 在衬底上形成硬掩模层; 去除所述硬掩模层的第一部分，其中所述硬掩模层的第二部分保留在所述至少一个栅极结构上; 以及通过所述硬掩模层的所述第二部分形成到所述至少一个栅极结构的第一接触，以及通过所述蚀刻停止层的所述第二部分到所述多个掺杂区域的第二接触。
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