公开(公告)号：US20190252191A1

公开(公告)日：2019-08-15

申请号：US16314601

申请日：2017-03-26

申请人： Dalian University of Technology

发明人： Hongwei LIANG ,  Xiaochuan XIA ,  Heqiu ZHANG

IPC分类号： H01L21/225

CPC分类号： H01L21/225 ,  H01L21/2258

摘要： The invention belongs to the technical field of semiconductor material preparation, and in particular provides a preparation method of tin doped n-type gallium oxide. To pre-deposit the appropriate tin doping source on gallium oxide materials in proper ways. The gallium oxide material is then placed in a high temperature tube in an appropriate manner. Then the tin atoms can be controlled to diffuse into the gallium oxide material by heat treatment at a certain temperature for a period of time. Then the tin atoms can be activated as an effective donor to realize the n-type doping of the gallium oxide material. In this invention, the doping can be realized after the preparation of the gallium oxide material is completed, and the necessary equipment and process are simple, and the doping controllability is high. The tin doping technique can not only fabricate the vertical structure device based on the n-type gallium oxide material, but also fabricate the transverse device structure and integrate various devices, so as to develop a new gallium oxide-based device which cannot be fabricated by the traditional doping technique.

公开(公告)号：US20180247832A1

公开(公告)日：2018-08-30

申请号：US15615691

申请日：2017-06-06

申请人： Lam Research Corporation

发明人： Andreas Fischer ,  Thorsten Lill ,  Richard Janek

IPC分类号： H01L21/3213 ,  H01L21/225 ,  H01L21/326 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/32136 ,  H01L21/0206 ,  H01L21/02068 ,  H01L21/225 ,  H01L21/31122 ,  H01L21/32138 ,  H01L21/326 ,  H01L21/67

摘要： A method for performing atomic layer etching (ALE) on a substrate is provided, including the following operations: performing a surface modification operation on a substrate surface, the surface modification operation configured to convert at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage configured to control a depth of the substrate surface that is converted by the surface modification operation; performing a removal operation on the substrate surface, the removal operation configured to remove at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer is effected via a ligand exchange reaction that is configured to volatilize the portion of the modified layer. A plasma treatment can be performed to remove residues from the substrate surface following the removal operation.

公开(公告)号：US10062777B2

公开(公告)日：2018-08-28

申请号：US15485892

申请日：2017-04-12

申请人： Texas Instruments Incorporated

发明人： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/51

CPC分类号： H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

摘要： A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US20180226257A1

公开(公告)日：2018-08-09

申请号：US15948297

申请日：2018-04-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takashi Ando ,  Mohit Bajaj ,  Terence B. Hook ,  Rajan K. Pandey ,  Rajesh Sathiyanarayanan

IPC分类号： H01L21/28 ,  H01L21/225 ,  H01L29/10 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/28185 ,  H01L21/0217 ,  H01L21/225 ,  H01L21/28176 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

摘要： A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.

公开(公告)号：US10002965B2

公开(公告)日：2018-06-19

申请号：US15298648

申请日：2016-10-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

摘要： A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US09947774B2

公开(公告)日：2018-04-17

申请号：US14925630

申请日：2015-10-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/225 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

摘要： A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US20180083064A1

公开(公告)日：2018-03-22

申请号：US15829551

申请日：2017-12-01

申请人： Arizona Board of Regents, Acting for and on Behalf of Arizona State University

发明人： Cun-Zheng Ning ,  Sunay Turkdogan ,  Zhicheng Liu ,  Fan Fan

IPC分类号： H01L27/15 ,  H01L33/00 ,  H01L21/02 ,  H01L33/28 ,  H01S5/30 ,  H01S5/40

CPC分类号： H01L27/15 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/04 ,  H01L21/225 ,  H01L21/265 ,  H01L27/153 ,  H01L33/005 ,  H01L33/0087 ,  H01L33/0095 ,  H01L33/28 ,  H01S5/3018 ,  H01S5/4093

摘要： Some embodiments include a method. The method can include: providing a carrier substrate; forming a first device material over the carrier substrate; and after forming the first device material over the carrier substrate, transforming the first device material into a second device material. Meanwhile, the transforming the first device material into the second device material can include: causing a cationic exchange in the first device material; and causing an anionic exchange in the first device material. The causing the cationic exchange in the first device material and the causing the anionic exchange in the first device material can occur approximately simultaneously. Other embodiments of related methods and systems are also disclosed.

公开(公告)号：US09923074B2

公开(公告)日：2018-03-20

申请号：US15629938

申请日：2017-06-22

申请人： International Business Machines Corporation

发明人： Chia-Yu Chen ,  Zuoguang Liu ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L21/225 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/08 ,  H01L21/311 ,  H01L29/49 ,  H01L21/3065 ,  H01L21/285 ,  H01L29/40 ,  H01L23/485

CPC分类号： H01L29/456 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/495 ,  H01L29/516 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

公开(公告)号：US09871125B2

公开(公告)日：2018-01-16

申请号：US15449199

申请日：2017-03-03

申请人： Infineon Technologies AG

发明人： Josef Boeck ,  Wolfgang Liebl

IPC分类号： H01L29/737 ,  H01L21/225 ,  H01L21/324 ,  H01L29/732 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/732 ,  H01L21/225 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/7371

摘要： A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.

公开(公告)号：US09847229B2

公开(公告)日：2017-12-19

申请号：US14706435

申请日：2015-05-07

申请人： Infineon Technologies AG

发明人： Hans-Joachim Schulze ,  Johannes Laven

IPC分类号： H01L21/02 ,  H01L21/225 ,  H01L21/266 ,  H01L27/04 ,  H01L29/36 ,  H01L21/265 ,  H01L29/66 ,  H01L29/739 ,  H01L29/861

CPC分类号： H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02395 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/225 ,  H01L21/266 ,  H01L27/04 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/861

摘要： A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.