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公开(公告)号:USD496343S1
公开(公告)日:2004-09-21
申请号:US29197089
申请日:2004-01-09
申请人: Yu-Mei Lin , Wen-Ming Wu , Michael M. Shen
设计人: Yu-Mei Lin , Wen-Ming Wu , Michael M. Shen
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公开(公告)号:USD508475S1
公开(公告)日:2005-08-16
申请号:US29207956
申请日:2004-06-21
申请人: Wen-Ming Wu , Yu-Mei Lin , Shu-Fen Ke
设计人: Wen-Ming Wu , Yu-Mei Lin , Shu-Fen Ke
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公开(公告)号:US20110110237A1
公开(公告)日:2011-05-12
申请号:US12880518
申请日:2010-09-13
申请人: Yuen Fai Wong , Yu-Mei Lin , Richard A. Grenier
发明人: Yuen Fai Wong , Yu-Mei Lin , Richard A. Grenier
IPC分类号: H04L12/54
CPC分类号: H04L47/2433 , H04L47/6275 , H04L49/30 , H04L49/352
摘要: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
摘要翻译: 一种方法和装置将来自第一处理器的多个输入数据流聚合成用于第二处理器的一个数据流,该电路和第一和第二处理器设置在电子电路基板上。 聚合电路包括(a)多个入口数据端口,每个入口数据端口适于从相应的第一处理器接收输入数据流,每个输入数据流由入口数据分组形成,每个入口数据分组包括其中编码的优先级因子 ,(b)耦合到所述入口数据端口的聚合模块,适于响应于所述优先级因素分析并组合所述多个输入数据流到一个聚合数据流中;(c)耦合到所述聚合模块的存储器,适于 存储分析的数据分组,以及(d)耦合到聚合模块的输出数据端口,适于将聚合的数据流输出到第二处理器。
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公开(公告)号:US08619781B2
公开(公告)日:2013-12-31
申请号:US13083481
申请日:2011-04-08
申请人: Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
发明人: Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
IPC分类号: H04L12/28
CPC分类号: H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
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5.
公开(公告)号:US07995580B2
公开(公告)日:2011-08-09
申请号:US12400594
申请日:2009-03-09
申请人: Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
发明人: Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
IPC分类号: H04L12/28
CPC分类号: H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
摘要翻译: 具有错误控制和冗余结构的背板接口适配器,用于高性能网络交换机。 错误控制可以由包括电平监视器,条带同步错误检测器,流量控制器和控制字符存在跟踪器的管理模块来提供。 背板接口适配器的冗余结构收发器改进了适配器正确和一致地接收携带数据分组的窄输入单元并将宽条带单元输出到交换结构的能力。
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公开(公告)号:US5632194A
公开(公告)日:1997-05-27
申请号:US740555
申请日:1996-10-30
申请人: Yu-Mei Lin
发明人: Yu-Mei Lin
CPC分类号: A47J31/0615 , A47J31/02
摘要: An infusion maker including a beaker having an inside annular flange in the middle, an inner cup mounted in the beaker for containing boiling water for steeping tea and having a bottom center through hole, a cap coupled to the inner cup at the bottom through a slip joint to hold a ball in a ball socket thereof, and a lid covered on the inner cup, the ball being forced to close the bottom center through hole of the inner cup when the inner cup is put in the beaker and supported on the inside annular flange of the beaker, the ball being disengaged from the bottom center through hole of the inner cup when the inner cup is lifted from the inside annular flange of the beaker, for permitting prepared tea infusion to flow out of the inner cup to the beaker.
摘要翻译: 一种输液器,其包括在中间具有内部环形凸缘的烧杯,安装在烧杯中的内杯,用于容纳用于浸泡茶的沸水并具有底部中心通孔,帽通过滑动件联接到底部的内杯 接头将球保持在其球窝中,盖子覆盖在内杯上,当内杯放入烧杯中时,球被迫关闭内杯的底部中心通孔,并支撑在内圈上 烧杯的凸缘,当内杯从烧杯的内部环形凸缘提升时,球从内杯的底部中心通孔脱离,以便准备的茶液从内杯流出至烧杯。
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公开(公告)号:US07948872B2
公开(公告)日:2011-05-24
申请号:US12400645
申请日:2009-03-09
申请人: Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
发明人: Ronak Patel , Ming G. Wong , Yu-Mei Lin , Andrew Chang , Yuen Fai Wong
IPC分类号: G06F11/00
CPC分类号: H04L45/74 , H04L47/50 , H04L47/6225 , H04L49/153 , H04L49/1538 , H04L49/25 , H04L49/30 , H04L49/3063 , H04L49/352 , H04L49/90 , H04L49/901
摘要: A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.
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公开(公告)号:USD545800S1
公开(公告)日:2007-07-03
申请号:US29245958
申请日:2005-12-29
申请人: Chia-Hsin Ou , Yu-Mei Lin , Ho-Tsung Hsueh
设计人: Chia-Hsin Ou , Yu-Mei Lin , Ho-Tsung Hsueh
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公开(公告)号:US07817659B2
公开(公告)日:2010-10-19
申请号:US10810208
申请日:2004-03-26
申请人: Yuen Fai Wong , Yu-Mei Lin , Richard A. Grenier
发明人: Yuen Fai Wong , Yu-Mei Lin , Richard A. Grenier
IPC分类号: H04L12/54
CPC分类号: H04L47/2433 , H04L47/6275 , H04L49/30 , H04L49/352
摘要: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
摘要翻译: 一种方法和装置将来自第一处理器的多个输入数据流聚合成用于第二处理器的一个数据流,该电路和第一和第二处理器设置在电子电路基板上。 聚合电路包括(a)多个入口数据端口,每个入口数据端口适于从相应的第一处理器接收输入数据流,每个输入数据流由入口数据分组形成,每个入口数据分组包括其中编码的优先级因子 ,(b)耦合到所述入口数据端口的聚合模块,适于响应于所述优先级因素分析并组合所述多个输入数据流到一个聚合数据流中;(c)耦合到所述聚合模块的存储器,适于 存储分析的数据分组,以及(d)耦合到聚合模块的输出数据端口,适于将聚合的数据流输出到第二处理器。
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公开(公告)号:US20090279559A1
公开(公告)日:2009-11-12
申请号:US10810208
申请日:2004-03-26
申请人: Yuen Fai Wong , Yu-Mei Lin , Richard A. Grenier
发明人: Yuen Fai Wong , Yu-Mei Lin , Richard A. Grenier
IPC分类号: H04L12/56
CPC分类号: H04L47/2433 , H04L47/6275 , H04L49/30 , H04L49/352
摘要: A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.
摘要翻译: 一种方法和装置将来自第一处理器的多个输入数据流聚合成用于第二处理器的一个数据流,该电路和第一和第二处理器设置在电子电路基板上。 聚合电路包括(a)多个入口数据端口,每个入口数据端口适于从相应的第一处理器接收输入数据流,每个输入数据流由入口数据分组形成,每个入口数据分组包括其中编码的优先级因子 ,(b)耦合到所述入口数据端口的聚合模块,适于响应于所述优先级因素分析并组合所述多个输入数据流到一个聚合数据流中;(c)耦合到所述聚合模块的存储器,适于 存储分析的数据分组,以及(d)耦合到聚合模块的输出数据端口,适于将聚合的数据流输出到第二处理器。
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