公开(公告)号：US20100073528A1

公开(公告)日：2010-03-25

申请号：US12236492

申请日：2008-09-23

申请人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang ,  Tsung-Chien Wu

发明人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang ,  Tsung-Chien Wu

IPC分类号： H04N5/52 ,  H04N5/20

CPC分类号： H04N5/365 ,  H04N5/243

摘要： A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.

摘要翻译： 提出了根据基于人眼的亮度灵敏度设置的增益查找表生成图像帧的增益的方法。 该方法包括将图像帧的增益设置为1，扫描图像帧的多个前排的图像，对图像帧的多个前行的图像进行平均，以生成图像的图像的平均值 多个图像帧的前排，根据图像帧的多个前排的图像的平均值，从增益的查找表中找到增益，并根据图像帧的剩余行调整 生成图像帧的剩余行的图像的增益。

公开(公告)号：US08009212B2

公开(公告)日：2011-08-30

申请号：US12237403

申请日：2008-09-25

申请人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang

发明人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/3742 ,  H04N5/365 ,  H04N5/378

摘要： Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.

摘要翻译： 提出了一种用于降低具有4-T（4晶体管）像素的图像处理系统中的固定模式噪声的电路及其方法。 图像处理系统包括两个电压源，两个电流源，4-T像素，线性化源极跟随器的第二部分，乒乓存储器，PGA和自动归零电路。 通过将自动归零电路耦合到PGA，形成开环，以在复位PGA时将PGA的运算放大器的输出钳位到稳定的参考电压，以便去除运放的输出端子处的直流偏移。

公开(公告)号：US08159557B2

公开(公告)日：2012-04-17

申请号：US12236492

申请日：2008-09-23

申请人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang ,  Tsung-Chien Wu

发明人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang ,  Tsung-Chien Wu

IPC分类号： H04N5/235

CPC分类号： H04N5/365 ,  H04N5/243

摘要： A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.

摘要翻译： 提出了根据基于人眼的亮度灵敏度设置的增益查找表生成图像帧的增益的方法。 该方法包括将图像帧的增益设置为1，扫描图像帧的多个前排的图像，对图像帧的多个前行的图像进行平均，以生成图像的图像的平均值 多个图像帧的前排，根据图像帧的多个前排的图像的平均值，从增益的查找表中找到增益，并根据图像帧的剩余行调整 生成图像帧的剩余行的图像的增益。

公开(公告)号：US20100073525A1

公开(公告)日：2010-03-25

申请号：US12237403

申请日：2008-09-25

申请人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang

发明人： Yuan-Che Lee ,  Jhy-Jyi Sze ,  Chiao-Fu Chang

IPC分类号： H04N5/21

CPC分类号： H04N5/3742 ,  H04N5/365 ,  H04N5/378

摘要： Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.

摘要翻译： 提出了一种用于降低具有4-T（4晶体管）像素的图像处理系统中的固定模式噪声的电路及其方法。 图像处理系统包括两个电压源，两个电流源，4-T像素，线性化源极跟随器的第二部分，乒乓存储器，PGA和自动归零电路。 通过将自动归零电路耦合到PGA，形成开环，以在复位PGA时将PGA的运算放大器的输出钳位到稳定的参考电压，以便去除运放的输出端子处的直流偏移。

公开(公告)号：US20090021266A1

公开(公告)日：2009-01-22

申请号：US11778635

申请日：2007-07-16

申请人： Chien-Kuo Wang ,  Tai-Chi Kao ,  Tsuoe-Hsiang Liao ,  Yuan-Che Lee ,  Yu-Ming Sun

发明人： Chien-Kuo Wang ,  Tai-Chi Kao ,  Tsuoe-Hsiang Liao ,  Yuan-Che Lee ,  Yu-Ming Sun

IPC分类号： H01L21/66 ,  G01R35/00

CPC分类号： G01R31/31717 ,  G01R31/2853 ,  G01R31/3191

摘要： A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

摘要翻译： 缺陷检测系统和相关方法利用多电平检测技术来检测集成电路上的缺陷。 缺陷检测系统利用模拟 - 数字转换器将模拟感测信号转换为具有多个位的输出码。 缺陷检测方法包括开放试验方法和短试验方法。 开放和短期测试方法都包括一种校准方法和一种测试方法。 校准方法用于基于预定代码确定模数转换器的预设参考电压。 测试方法利用预设的参考电压和用于生成具有多个位的输出代码的预定代码。 然后使用输出代码来确定集成电路上是否存在开路或短路缺陷，并对缺陷进行分类。

公开(公告)号：US07808308B2

公开(公告)日：2010-10-05

申请号：US12372136

申请日：2009-02-17

申请人： Cheng-Hsiao Lai ,  Yuan-Che Lee ,  Tsung-Chien Wu

发明人： Cheng-Hsiao Lai ,  Yuan-Che Lee ,  Tsung-Chien Wu

IPC分类号： G05F1/10

CPC分类号： G05F3/30 ,  G05F3/24

摘要： A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

摘要翻译： 公开了一种电压产生装置。 电压产生装置包括第一N型晶体管和增强型MOSFET晶体管。 第一N型晶体管具有耦合到第一电压的第一漏极/源极，产生第一输出电压的第二漏极/源极和耦合到第二电压的栅极。 增强型MOSFET晶体管具有耦合到第一N型晶体管的第二漏极/源极的第一漏极/源极，以及耦合到第二电压的第二漏极/源极和栅极。 第一N型晶体管是耗尽金属氧化物半导体场效应晶体管（MOSFET）。

公开(公告)号：US20100207686A1

公开(公告)日：2010-08-19

申请号：US12372136

申请日：2009-02-17

申请人： Cheng-Hsiao Lai ,  Yuan-Che Lee ,  Tsung-Chien Wu

发明人： Cheng-Hsiao Lai ,  Yuan-Che Lee ,  Tsung-Chien Wu

IPC分类号： G05F1/20 ,  G05F3/24

CPC分类号： G05F3/30 ,  G05F3/24

摘要： A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

摘要翻译： 公开了一种电压产生装置。 电压产生装置包括第一N型晶体管和增强型MOSFET晶体管。 第一N型晶体管具有耦合到第一电压的第一漏极/源极，产生第一输出电压的第二漏极/源极和耦合到第二电压的栅极。 增强型MOSFET晶体管具有耦合到第一N型晶体管的第二漏极/源极的第一漏极/源极，以及耦合到第二电压的第二漏极/源极和栅极。 第一N型晶体管是耗尽金属氧化物半导体场效应晶体管（MOSFET）。

公开(公告)号：US07646203B2

公开(公告)日：2010-01-12

申请号：US11778635

申请日：2007-07-16

申请人： Chien-Kuo Wang ,  Tai-Chi Kao ,  Tsuoe-Hsiang Liao ,  Yuan-Che Lee ,  Yu-Ming Sun

发明人： Chien-Kuo Wang ,  Tai-Chi Kao ,  Tsuoe-Hsiang Liao ,  Yuan-Che Lee ,  Yu-Ming Sun

IPC分类号： H01H31/02

CPC分类号： G01R31/31717 ,  G01R31/2853 ,  G01R31/3191

摘要： A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

摘要翻译： 缺陷检测系统和相关方法利用多电平检测技术来检测集成电路上的缺陷。 缺陷检测系统利用模拟 - 数字转换器将模拟感测信号转换为具有多个位的输出码。 缺陷检测方法包括开放试验方法和短试验方法。 开放和短期测试方法都包括一种校准方法和一种测试方法。 校准方法用于基于预定代码确定模数转换器的预设参考电压。 测试方法利用预设的参考电压和用于生成具有多个位的输出代码的预定代码。 然后使用输出代码来确定集成电路上是否存在开路或短路缺陷，并对缺陷进行分类。