Voltage generating apparatus
    1.
    发明授权
    Voltage generating apparatus 有权
    电压发生装置

    公开(公告)号:US07808308B2

    公开(公告)日:2010-10-05

    申请号:US12372136

    申请日:2009-02-17

    IPC分类号: G05F1/10

    CPC分类号: G05F3/30 G05F3/24

    摘要: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

    摘要翻译: 公开了一种电压产生装置。 电压产生装置包括第一N型晶体管和增强型MOSFET晶体管。 第一N型晶体管具有耦合到第一电压的第一漏极/源极,产生第一输出电压的第二漏极/源极和耦合到第二电压的栅极。 增强型MOSFET晶体管具有耦合到第一N型晶体管的第二漏极/源极的第一漏极/源极,以及耦合到第二电压的第二漏极/源极和栅极。 第一N型晶体管是耗尽金属氧化物半导体场效应晶体管(MOSFET)。

    VOLTAGE GENERATING APPARATUS
    2.
    发明申请
    VOLTAGE GENERATING APPARATUS 有权
    电压发生装置

    公开(公告)号:US20100207686A1

    公开(公告)日:2010-08-19

    申请号:US12372136

    申请日:2009-02-17

    IPC分类号: G05F1/20 G05F3/24

    CPC分类号: G05F3/30 G05F3/24

    摘要: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

    摘要翻译: 公开了一种电压产生装置。 电压产生装置包括第一N型晶体管和增强型MOSFET晶体管。 第一N型晶体管具有耦合到第一电压的第一漏极/源极,产生第一输出电压的第二漏极/源极和耦合到第二电压的栅极。 增强型MOSFET晶体管具有耦合到第一N型晶体管的第二漏极/源极的第一漏极/源极,以及耦合到第二电压的第二漏极/源极和栅极。 第一N型晶体管是耗尽金属氧化物半导体场效应晶体管(MOSFET)。

    METHOD OF GENERATING A GAIN OF AN IMAGE FRAME
    3.
    发明申请
    METHOD OF GENERATING A GAIN OF AN IMAGE FRAME 有权
    产生图像帧增益的方法

    公开(公告)号:US20100073528A1

    公开(公告)日:2010-03-25

    申请号:US12236492

    申请日:2008-09-23

    IPC分类号: H04N5/52 H04N5/20

    CPC分类号: H04N5/365 H04N5/243

    摘要: A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.

    摘要翻译: 提出了根据基于人眼的亮度灵敏度设置的增益查找表生成图像帧的增益的方法。 该方法包括将图像帧的增益设置为1,扫描图像帧的多个前排的图像,对图像帧的多个前行的图像进行平均,以生成图像的图像的平均值 多个图像帧的前排,根据图像帧的多个前排的图像的平均值,从增益的查找表中找到增益,并根据图像帧的剩余行调整 生成图像帧的剩余行的图像的增益。

    Method of generating a gain of an image frame
    4.
    发明授权
    Method of generating a gain of an image frame 有权
    产生图像帧增益的方法

    公开(公告)号:US08159557B2

    公开(公告)日:2012-04-17

    申请号:US12236492

    申请日:2008-09-23

    IPC分类号: H04N5/235

    CPC分类号: H04N5/365 H04N5/243

    摘要: A method of generating a gain of an image frame according to a look up table of gain which is set up based on luminance sensitivity of human eyes is proposed. The method includes setting a gain of an image frame to 1, scanning images of a plurality of front rows of the image frame, averaging the images of the plurality of the front rows of the image frame to generate an average value of the images of the plurality of the front rows of the image frame, finding a gain from the look up table of gain according to the average value of the images of the plurality of the front rows of the image frame, and adjusting remaining rows of the image frame according to the gain to generate images of the remaining rows of the image frame.

    摘要翻译: 提出了根据基于人眼的亮度灵敏度设置的增益查找表生成图像帧的增益的方法。 该方法包括将图像帧的增益设置为1,扫描图像帧的多个前排的图像,对图像帧的多个前行的图像进行平均,以生成图像的图像的平均值 多个图像帧的前排,根据图像帧的多个前排的图像的平均值,从增益的查找表中找到增益,并根据图像帧的剩余行调整 生成图像帧的剩余行的图像的增益。

    PHASE LOCKED LOOP AND METHOD THEREOF
    5.
    发明申请
    PHASE LOCKED LOOP AND METHOD THEREOF 有权
    相位锁定环路及其方法

    公开(公告)号:US20080224789A1

    公开(公告)日:2008-09-18

    申请号:US11686092

    申请日:2007-03-14

    IPC分类号: H03C3/06 H03L7/00

    摘要: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

    摘要翻译: 在锁相环(PLL)中,移相器移位输入信号的相位。 基于输入信号的相位,移位的信号和分频输出信号,相位频率检测器(PFD)产生相位差信号。 响应于相位差信号,电荷泵(CP)控制其输出电压。 基于CP的输出电压,压控振荡器(VCO)输出输出信号。 分频器分频来自VCO的输出信号的频率,以产生分频输出信号。 循环器在正确的时机将分频输出信号输出到一个PFD。 调制器减少了分频器的量化误差。

    LAYOUT OF POWER DEVICE
    6.
    发明申请
    LAYOUT OF POWER DEVICE 有权
    电力设备布局

    公开(公告)号:US20080174371A1

    公开(公告)日:2008-07-24

    申请号:US11626013

    申请日:2007-01-23

    IPC分类号: H03F3/14 H03F3/68

    摘要: A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

    摘要翻译: 提供电源设备的布局。 布局包括基板,单元阵列,多个第一,第二,第三和第四信号路径以及第一,第二,第三和第四端口。 具有多行的单元阵列设置在基板上。 单元阵列的每一行包括多个单元。 衬底上的第一和第二信号路径被布置在单元阵列的相应奇数行的第一侧和第二侧上。 衬底上的第三和第四信号路径设置在单元阵列的相应行上方。 基板上的第一至第四端口分别电连接到第一至第四信号路径。

    Phase locked loop with phase shifted input
    7.
    发明授权
    Phase locked loop with phase shifted input 有权
    带相移输入的锁相环

    公开(公告)号:US07636018B2

    公开(公告)日:2009-12-22

    申请号:US11686092

    申请日:2007-03-14

    IPC分类号: H03L7/00

    摘要: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

    摘要翻译: 在锁相环(PLL)中,移相器移位输入信号的相位。 基于输入信号的相位,移位的信号和分频输出信号,相位频率检测器(PFD)产生相位差信号。 响应于相位差信号,电荷泵(CP)控制其输出电压。 基于CP的输出电压,压控振荡器(VCO)输出输出信号。 分频器分频来自VCO的输出信号的频率,以产生分频输出信号。 循环器在正确的时机将分频输出信号输出到一个PFD。 调制器减少了分频器的量化误差。

    Layout of power device
    8.
    发明授权
    Layout of power device 有权
    电源设备布局

    公开(公告)号:US07571415B2

    公开(公告)日:2009-08-04

    申请号:US11626013

    申请日:2007-01-23

    IPC分类号: G06F17/50 H01L27/088 H03F1/00

    摘要: A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

    摘要翻译: 提供电源设备的布局。 布局包括基板,单元阵列,多个第一,第二,第三和第四信号路径以及第一,第二,第三和第四端口。 具有多行的单元阵列设置在基板上。 单元阵列的每一行包括多个单元。 衬底上的第一和第二信号路径被布置在单元阵列的相应奇数行的第一侧和第二侧上。 衬底上的第三和第四信号路径设置在单元阵列的相应行上方。 基板上的第一至第四端口分别电连接到第一至第四信号路径。