公开(公告)号：US08222136B2

公开(公告)日：2012-07-17

申请号：US12906868

申请日：2010-10-18

申请人： Yuan-Tien Tu ,  Tsai-Chun Li ,  Huan-Just Lin ,  Shih-Chang Chen

发明人： Yuan-Tien Tu ,  Tsai-Chun Li ,  Huan-Just Lin ,  Shih-Chang Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76816

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成层。 所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。 该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。 该方法包括用导电材料填充第一开口。 所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。 该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。 第一和第二溅射工艺之一比另一个更强大。

公开(公告)号：US20120094485A1

公开(公告)日：2012-04-19

申请号：US12906868

申请日：2010-10-18

申请人： Yuan-Tien Tu ,  Tsai-Chun Li ,  Huan-Just Lin ,  Shih-Chang Chen

发明人： Yuan-Tien Tu ,  Tsai-Chun Li ,  Huan-Just Lin ,  Shih-Chang Chen

IPC分类号： H01L21/28

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76816

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成层。 所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。 该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。 该方法包括用导电材料填充第一开口。 所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。 该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。 第一和第二溅射工艺之一比另一个更强大。

公开(公告)号：US08546227B2

公开(公告)日：2013-10-01

申请号：US13289112

申请日：2011-11-04

申请人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

发明人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

摘要翻译： 制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。 在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。 在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。 在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。 然后用导电材料填充沟槽和底切。

公开(公告)号：US20130069174A1

公开(公告)日：2013-03-21

申请号：US13289112

申请日：2011-11-04

申请人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

发明人： Hak-Lay Chuang ,  Sheng-Chen Chung ,  Wei Cheng Wu ,  Bao-Ru Young ,  Huan-Just Lin ,  Tsai-Chun Li

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28114 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/823842 ,  H01L29/41775 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

摘要翻译： 制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。 在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。 在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。 在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。 然后用导电材料填充沟槽和底切。

公开(公告)号：US20070134917A1

公开(公告)日：2007-06-14

申请号：US11301917

申请日：2005-12-13

申请人： Tsai-Chun Li ,  Tsang-Jiuh Wu ,  Hui Ouyang

发明人： Tsai-Chun Li ,  Tsang-Jiuh Wu ,  Hui Ouyang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7681 ,  H01L21/76813

摘要： A partial-via-first dual-damascene method using a tri-layer resist method forms a first via hole through partial thickness of a dielectric layer, and forms a tri-layer resist structure on the dielectric layer to fill the first via hole with the bottom photoresist layer. A dry development process is performed to transfer a first opening on the top photoresist layer to the middle layer and the bottom photoresist layer, and expose the first via hole again, and remove the top photoresist layer. A dry etching process is then performed to form a second via hole under the first via hole and a trench over the second via hole. Finally a wet striping process is used to remove the remainder of the photoresist layer.

摘要翻译： 使用三层抗蚀剂法的部分通孔 - 第一双镶嵌法通过介电层的部分厚度形成第一通孔，并在介电层上形成三层抗蚀剂结构，以填充第一通孔 底部光刻胶层。 进行干式显影处理以将顶部光致抗蚀剂层上的第一开口转移到中间层和底部光致抗蚀剂层，并再次暴露第一通孔，并除去顶部光致抗蚀剂层。 然后执行干蚀刻工艺以在第一通孔下方形成第二通孔，并在第二通孔上形成沟槽。 最后，使用湿条纹工艺去除光致抗蚀剂层的其余部分。