公开(公告)号：US20080179676A1

公开(公告)日：2008-07-31

申请号：US11971434

申请日：2008-01-09

申请人： Yuichi HIRANO ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yukio Maki ,  Mikio Tsujiuchi

发明人： Yuichi HIRANO ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yukio Maki ,  Mikio Tsujiuchi

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

摘要： While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.

摘要翻译： 在减小SRAM单元的形成面积的同时，抑制了各个晶体管的电特性的变化。 在SOI板中形成的SRAM单元中，驱动晶体管（其也是存取晶体管的源极/漏极区域）的漏极区域与负载晶体管的漏极区域之间的电耦合以及电耦合 另一个驱动晶体管的漏极区（也是另一个存取晶体管的源极/漏极区）和另一个负载晶体管的漏极区通过在隔离氧化膜下使用SOI层而形成的布线结构来建立，该SOI层是部分沟槽隔离 ， 分别。

公开(公告)号：US20120306001A1

公开(公告)日：2012-12-06

申请号：US13471949

申请日：2012-05-15

申请人： Yuichi HIRANO

发明人： Yuichi HIRANO

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

摘要： A semiconductor device includes a semiconductor substrate having a main surface, a MONOS-type memory cell formed over the main surface and having a channel, an n-channel transistor formed over the main surface, and a p-channel transistor formed over the man surface. Nitride films are formed in a manner to contact the top surfaces of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor. The nitride films apply stress to the channels of the MONOS-type memory cell, the n-channel transistor, and the p-channel transistor.

摘要翻译： 半导体器件包括具有主表面的半导体衬底，形成在主表面上并具有通道的MONOS型存储单元，形成在主表面上的n沟道晶体管和形成在主表面上的p沟道晶体管 。 氮化物膜以与MONOS型存储单元，n沟道晶体管和p沟道晶体管的顶面接触的方式形成。 氮化物膜对MONOS型存储单元，n沟道晶体管和p沟道晶体管的沟道施加应力。

公开(公告)号：US20120061767A1

公开(公告)日：2012-03-15

申请号：US13186163

申请日：2011-07-19

申请人： Yuichi HIRANO

发明人： Yuichi HIRANO

IPC分类号： H01L27/092 ,  H01L21/425

CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/82385

摘要： A semiconductor device includes core transistors for forming a logic circuit, and I/O transistors for forming an input/output circuit. A distance from the main surface to a lowermost part of an n-type impurity region NR of the I/O n-type transistor is longer than that from the main surface to a lowermost part of an n-type impurity region NR of the core n-type transistor. A distance from the main surface to a lowermost part of a p-type impurity region PR of the I/O p-type transistor is longer than that from the main surface to a lowermost part of a p-type impurity region of the core p-type transistor. A distance from the main surface to the lowermost part of the n-type impurity region of the I/O n-type transistor is longer than that from the main surface to the lowermost part of the p-type impurity region of the I/O p-type transistor.

摘要翻译： 半导体器件包括用于形成逻辑电路的核心晶体管和用于形成输入/输出电路的I / O晶体管。 从I / O型晶体管的n型杂质区NR的主表面到最下部的距离比从芯的n型杂质区NR的主表面到最下部的距离长 n型晶体管。 I / O p型晶体管的p型杂质区PR的主表面到最下部的距离比从芯p的p型杂质区的主表面到最下部的距离长 型晶体管。 从I / O型晶体管的n型杂质区域的主表面到最下部分的距离比从I / O的p型杂质区域的主表面到最下部分的长 p型晶体管。

公开(公告)号：US20100314686A1

公开(公告)日：2010-12-16

申请号：US12861038

申请日：2010-08-23

申请人： Yuichi HIRANO

发明人： Yuichi HIRANO

IPC分类号： H01L27/12

CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

摘要翻译： 栅电极被设置为使得其栅极宽度方向上的两端在平面视图中从有源区域突出。 部分沟槽隔离绝缘膜设置在对应于两端的下部的SOI衬底的表面中，并且在栅极宽度方向上的栅极电极的外侧的SOI衬底的表面中设置体接触区域， 与相应的部分沟槽隔离绝缘膜相邻。 体接触区域和体区域在部分沟槽隔离绝缘膜下通过SOI层（阱区）电连接。 此外，在栅极中心附近的源极区域的栅极宽度方向的表面设置有以较高浓度掺杂有P型杂质的源极连接区域。

公开(公告)号：US20070241402A1

公开(公告)日：2007-10-18

申请号：US11733454

申请日：2007-04-10

申请人： Yuichi HIRANO

发明人： Yuichi HIRANO

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

摘要翻译： 栅电极被设置为使得其栅极宽度方向上的两端在平面视图中从有源区域突出。 部分沟槽隔离绝缘膜设置在对应于两端的下部的SOI衬底的表面中，并且在栅极宽度方向上的栅极电极的外侧的SOI衬底的表面中设置体接触区域， 与相应的部分沟槽隔离绝缘膜相邻。 体接触区域和体区域在部分沟槽隔离绝缘膜下通过SOI层（阱区）电连接。 此外，在栅极中心附近的源极区域的栅极宽度方向的表面设置有以较高浓度掺杂有P型杂质的源极连接区域。