公开(公告)号：US20100035428A1

公开(公告)日：2010-02-11

申请号：US12535665

申请日：2009-08-04

申请人： Yuichi NAKAO ,  Satoshi Kageyama ,  Yoshihisa Takada

发明人： Yuichi NAKAO ,  Satoshi Kageyama ,  Yoshihisa Takada

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.

摘要翻译： 根据本发明的制造半导体器件的方法包括：沟槽形成步骤，在由含有Si和O的绝缘材料制成的绝缘层中形成沟槽; 合金膜施加步骤，用溅射对含有Cu和Mn的合金材料制成的合金膜覆盖槽的侧面和底面; 减薄覆盖槽的底面的合金膜的一部分的厚度的薄化步骤; 线形成步骤，在所述变薄步骤之后，在所述槽中形成由主要由Cu构成的金属材料制成的Cu线; 以及通过热处理在Cu线和绝缘层之间形成由MnSiO制成的阻挡膜的阻挡膜形成步骤。

公开(公告)号：US08039390B2

公开(公告)日：2011-10-18

申请号：US12535665

申请日：2009-08-04

申请人： Yuichi Nakao ,  Satoshi Kageyama ,  Yoshihisa Takada

发明人： Yuichi Nakao ,  Satoshi Kageyama ,  Yoshihisa Takada

IPC分类号： H01L21/68

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The method of manufacturing a semiconductor device according to the present invention includes: a groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O; an alloy film applying step of covering the side surface and the bottom surface of the groove with an alloy film made of an alloy material containing Cu and Mn by sputtering; a thinning step of reducing the thickness of a portion of the alloy film covering the bottom surface of the groove; a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu in the groove after the thinning step; and a barrier film forming step of forming a barrier film made of MnSiO between the Cu wire and the insulating layer by heat treatment.

摘要翻译： 根据本发明的制造半导体器件的方法包括：沟槽形成步骤，在由含有Si和O的绝缘材料制成的绝缘层中形成沟槽; 合金膜施加步骤，用溅射对含有Cu和Mn的合金材料制成的合金膜覆盖槽的侧面和底面; 减薄覆盖槽的底面的合金膜的一部分的厚度的薄化步骤; 线形成步骤，在所述变薄步骤之后，在所述槽中形成由主要由Cu构成的金属材料制成的Cu线; 以及通过热处理在Cu线和绝缘层之间形成由MnSiO制成的阻挡膜的阻挡膜形成步骤。

公开(公告)号：US20090189282A1

公开(公告)日：2009-07-30

申请号：US12318862

申请日：2009-01-09

申请人： Yoshihisa Takada ,  Satoshi Kageyama

发明人： Yoshihisa Takada ,  Satoshi Kageyama

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a low dielectric layer made of a low dielectric material; a high dielectric layer formed on the low dielectric layer and made of a high dielectric material having a higher dielectric constant than the low dielectric material; a protective layer formed on the high dielectric layer and made of an insulating material differing from the low dielectric material and the high dielectric material; a groove formed by digging in from an upper surface of the protective layer to the low dielectric layer; a barrier film coated onto a bottom surface and side surfaces of the groove and made of a material having a barrier property with respect to diffusion of Cu; and a wiring formed on the barrier film, made of a metal material having Cu as a main component, and completely filling the groove.

摘要翻译： 根据本发明的半导体器件包括：由低介电材料制成的低介电层; 形成在低介电层上并由具有比低电介质材料更高的介电常数的高电介质材料制成的高介电层; 形成在高电介质层上并由不同于低电介质材料和高电介质材料的绝缘材料制成的保护层; 通过从所述保护层的上表面向所述低介电层进行挖掘而形成的槽; 阻挡膜涂覆在槽的底表面和侧表面上，并且由相对于Cu的扩散具有阻挡性的材料制成; 以及形成在由Cu作为主要成分的金属材料制成的阻挡膜上并且完全填充槽的布线。

公开(公告)号：US08164197B2

公开(公告)日：2012-04-24

申请号：US12222309

申请日：2008-08-06

申请人： Yuichi Nakao ,  Satoshi Kageyama

发明人： Yuichi Nakao ,  Satoshi Kageyama

IPC分类号： H01L23/535

CPC分类号： H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric film to intersect with a prescribed portion of the lower wire in plan view. The first interlayer dielectric film is provided with a groove dug from the upper surface thereof in a region including the prescribed portion in plan view. The prescribed portion enters the groove. At least a portion of the second interlayer dielectric film formed on the lower wire has a planar upper surface.

摘要翻译： 根据本发明的半导体器件包括：第一层间电介质膜; 形成在所述第一层间电介质膜上的下线; 形成在第一层间电介质膜和下导线上的第二层间绝缘膜; 以及形成在第二层间电介质膜上的上部线，在平面图中与下部电线的规定部分相交。 第一层间电介质膜在平面图中包括从规定部分的区域中从其上表面挖出的沟槽。 规定部分进入凹槽。 形成在下导线上的第二层间绝缘膜的至少一部分具有平坦的上表面。

公开(公告)号：US20100032837A1

公开(公告)日：2010-02-11

申请号：US12445168

申请日：2007-10-11

申请人： Ryosuke Nakagawa ,  Takahisa Yamaha ,  Yuichi Nakao ,  Katsumi Sameshima ,  Satoshi Kageyama

发明人： Ryosuke Nakagawa ,  Takahisa Yamaha ,  Yuichi Nakao ,  Katsumi Sameshima ,  Satoshi Kageyama

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/2855 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion of the barrier layer defined between the boundary portions.

摘要翻译： 根据本发明的半导体器件包括：半导体衬底; 设置在半导体衬底上的第一铜互连; 绝缘层，设置在所述第一铜互连上并且具有穿过其延伸到所述第一铜互连的孔; 由含钽材料构成并且覆盖所述孔的至少一个侧壁和暴露在所述孔中的所述第一铜互连的一部分的阻挡层; 以及第二铜互连，其与阻挡层紧密接触并且经由阻挡层电连接到第一铜互连; 其中所述阻挡层具有氮浓度分布，使得所述材料中包含的氮的浓度在与所述第一铜互连相邻的所述阻挡层的边界部分中以及在与所述第二铜互连相邻的所述势垒层的边界部分中变低 铜互连并且在边界部分之间限定的阻挡层的中间部分中较高。

公开(公告)号：US08508033B2

公开(公告)日：2013-08-13

申请号：US13067154

申请日：2011-05-12

申请人： Satoshi Kageyama ,  Yuichi Nakao

发明人： Satoshi Kageyama ,  Yuichi Nakao

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.

摘要翻译： 根据本发明的半导体器件包括半导体层，形成在半导体层上的层间电介质膜，在具有宽度不大于0.4μm的金属材料的层间绝缘膜上形成的导线，以及广泛部分 一体形成在金属丝上，从金属丝沿其宽度方向延伸。

公开(公告)号：US08110504B2

公开(公告)日：2012-02-07

申请号：US12536472

申请日：2009-08-05

申请人： Yuichi Nakao ,  Satoshi Kageyama

发明人： Yuichi Nakao ,  Satoshi Kageyama

IPC分类号： H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L2221/1089

摘要： The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.

摘要翻译： 根据本发明的制造半导体器件的方法包括：绝缘层形成步骤，形成由包含Si和O的绝缘材料制成的绝缘层; 在所述绝缘层中形成槽的槽形成工序; 通过溅射用MnO x（x：数大于零）的金属膜覆盖槽的内表面的金属膜施加步骤; 以及在金属膜上形成由主要由Cu构成的金属材料制成的Cu线的线形成工序。

公开(公告)号：US09082769B2

公开(公告)日：2015-07-14

申请号：US13367964

申请日：2012-02-07

申请人： Satoshi Kageyama ,  Yuichi Nakao

发明人： Satoshi Kageyama ,  Yuichi Nakao

IPC分类号： H01L23/52 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L23/5256 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5223 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.

摘要翻译： 半导体器件包括由导电材料制成的下布线层; 上层布线层，形成在上层中，比下布线层形成; 以及熔丝膜，所述熔丝膜的至少一部分形成在其中形成用于连接所述下布线层和所述上布线层的插塞的插塞形成层中，并且由包含除了所述下布线层和所述上布线层之外的金属材料的导电材料制成 铜。

公开(公告)号：US08647984B2

公开(公告)日：2014-02-11

申请号：US13345046

申请日：2012-01-06

申请人： Yuichi Nakao ,  Satoshi Kageyama

发明人： Yuichi Nakao ,  Satoshi Kageyama

IPC分类号： H01L21/44

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L2221/1089

摘要： The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.

摘要翻译： 根据本发明的制造半导体器件的方法包括：绝缘层形成步骤，形成由包含Si和O的绝缘材料制成的绝缘层; 在所述绝缘层中形成槽的槽形成工序; 通过溅射用MnO x（x：数大于零）的金属膜覆盖槽的内表面的金属膜施加步骤; 以及在金属膜上形成由主要由Cu构成的金属材料制成的Cu线的线形成工序。

公开(公告)号：US20120108059A1

公开(公告)日：2012-05-03

申请号：US13345046

申请日：2012-01-06

申请人： Yuichi NAKAO ,  Satoshi Kageyama

发明人： Yuichi NAKAO ,  Satoshi Kageyama

IPC分类号： H01L21/768

CPC分类号： H01L21/76844 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L2221/1089

摘要： The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.

摘要翻译： 根据本发明的制造半导体器件的方法包括：绝缘层形成步骤，形成由包含Si和O的绝缘材料制成的绝缘层; 在所述绝缘层中形成槽的槽形成工序; 通过溅射用MnO x（x：数大于零）的金属膜覆盖槽的内表面的金属膜施加步骤; 以及在金属膜上形成由主要由Cu构成的金属材料制成的Cu线的线形成工序。