公开(公告)号：US08299564B1

公开(公告)日：2012-10-30

申请号：US12559457

申请日：2009-09-14

申请人： Yun Wu ,  Bei Zhu ,  Zhiyuan Wu ,  Michael J. Hart

发明人： Yun Wu ,  Bei Zhu ,  Zhiyuan Wu ,  Michael J. Hart

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： Formation of transistors, such as, e.g., PMOS transistors, with diffusion regions having different depths for equalization of performance among transistors of an integrated circuit is described. Shallow-trench isolation structures are formed in a substrate formed at least in part of silicon for providing the transistors with at least substantially equivalent channel widths and lengths. A series of masks and etches is performed to form first recesses and second recesses defined in the silicon having different depths and respectively associated with first and second transistors. The second recesses are deeper than the first recesses. A silicon germanium film is formed in the first recesses and the second recesses. The silicon germanium film in the second recesses is thicker than the silicon germanium film in the first recesses, in order to increase performance of the second transistor so it is closer to the performance of the first transistor.

摘要翻译： 描述了具有扩散区域的诸如PMOS晶体管的晶体管的形成，其具有用于集成电路的晶体管之间的性能均衡的不同深度。 浅沟槽隔离结构形成在至少部分硅中形成的衬底中，用于为晶体管提供至少基本相当的沟道宽度和长度。 执行一系列掩模和蚀刻以形成在具有不同深度并且分别与第一和第二晶体管相关联的硅中限定的第一凹部和第二凹部。 第二凹部比第一凹部更深。 在第一凹部和第二凹部中形成硅锗膜。 第二凹部中的硅锗膜比第一凹部中的硅锗膜厚，以便增加第二晶体管的性能，使得其更接近于第一晶体管的性能。

公开(公告)号：US08350253B1

公开(公告)日：2013-01-08

申请号：US12697027

申请日：2010-01-29

申请人： Bei Zhu ,  Hong-Tze Pan ,  Bang-Thu Nguyen ,  Qi Lin ,  Zhiyuan Wu ,  Ping-Chin Yeh ,  Jae-Gyung Ahn ,  Yun Wu

发明人： Bei Zhu ,  Hong-Tze Pan ,  Bang-Thu Nguyen ,  Qi Lin ,  Zhiyuan Wu ,  Ping-Chin Yeh ,  Jae-Gyung Ahn ,  Yun Wu

IPC分类号： H01L29/06

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/7848

摘要： An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

摘要翻译： 在半导体衬底上制造的集成电路（IC）具有形成在半导体衬底中的沟道区上的有源栅极结构。 在绝缘隔离结构上形成虚拟栅极结构。 虚拟栅极结构和有源栅极结构具有相同的宽度。 虚拟栅极结构上的侧壁间隔物覆盖在应变诱导插入件和介电隔离结构之间的半导体部分。

公开(公告)号：US08302064B1

公开(公告)日：2012-10-30

申请号：US12401450

申请日：2009-03-10

申请人： Sharmin Sadoughi ,  Prabhuram Gopalan ,  Michael J. Hart ,  John Cooksey ,  Zhiyuan Wu

发明人： Sharmin Sadoughi ,  Prabhuram Gopalan ,  Michael J. Hart ,  John Cooksey ,  Zhiyuan Wu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5072

摘要： Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.

摘要翻译： 选择性地改变诸如栅极长度和沟道宽度的器件特征，首先识别半导体管芯内的这些器件，其显示物理属性，例如泄漏电流和阈值电压幅度，其不同于先前使用的设计/仿真工具验证 设计设备。 然后，通过与每个不合格设备展示的原始设计目标的偏差量进一步识别所识别的不合格设备。 然后将不合格的设备数学分类成箱体，其中每个箱体标记有与设计目标的偏差幅度。 然后，限定不合格装置的特征的掩模层被选择性地修改与标记偏差相当的量。 然后使用选择性修改的掩模层来产生表现出改善的性能的新的半导体管芯。

公开(公告)号：US07793238B1

公开(公告)日：2010-09-07

申请号：US12053874

申请日：2008-03-24

申请人： Peter Rabkin ,  Zhiyuan Wu ,  Min-Hsing Peter Chen ,  Jane W. Sowards ,  Michael J. Hart ,  Min-Fang Ho

发明人： Peter Rabkin ,  Zhiyuan Wu ,  Min-Hsing Peter Chen ,  Jane W. Sowards ,  Michael J. Hart ,  Min-Fang Ho

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Various approaches for improving an integrated circuit layout. In one approach, a tree-type hierarchical layout representation of the circuit design is traversed. At each block visited during the traversing, a process determines whether there exists an improvement opportunity for each cell associated with the block. In response to determining that an improvement opportunity exists for a cell of a first block of the plurality of blocks, the process determines whether a modification to the cell satisfies one or more rules for every other block of the block type of the first block in the hierarchical representation. If the rules are satisfied, the modification is stored. Otherwise, the modification is discarded.

摘要翻译： 用于改善集成电路布局的各种方法。 在一种方法中，遍历了电路设计的树型分层布局表示。 在遍历期间访问的每个块处，确定是否存在与该块相关联的每个单元的改进机会。 响应于确定对于所述多个块的第一块的小区存在改进机会，所述过程确定对所述小区的修改是否满足所述小区的所述第一块的块类型的每个其他块的一个或多个规则 分层表示。 如果规则满足，则修改被存储。 否则，修改被丢弃。

公开(公告)号：US20150039292A1

公开(公告)日：2015-02-05

申请号：US14233640

申请日：2012-07-19

申请人： Kaheer Suleman ,  Joshua R. Pantony ,  Wilson Hsu ,  Zhiyuan Wu ,  Phil Tregenza ,  Sam Paspupalak

发明人： Kaheer Suleman ,  Joshua R. Pantony ,  Wilson Hsu ,  Zhiyuan Wu ,  Phil Tregenza ,  Sam Paspupalak

IPC分类号： G06F17/30 ,  G06F3/16 ,  G06F17/28

CPC分类号： G06F16/245 ,  G06F3/16 ,  G06F3/167 ,  G06F16/285 ,  G06F17/28 ,  G06F17/289 ,  G06Q30/0601 ,  G10L15/1822

摘要： A method and system are provided for processing natural language user queries for commanding a user interface to perform functions. Individual user queries are classified in accordance with the types of functions and a plurality of user queries may be related to define a particular command. To assist with classification, a query type for each user query is determined where the query type is one of a functional query requesting a particular new command to perform a particular type of function, an entity query relating to an entity associated with the particular new command having the particular type of function and a clarification query responding to a clarification question posed to clarify a prior user query having the particular type of function. Functional queries may be processed using a plurality of natural language processing techniques and scores from each technique combined to determine which type of function is commanded.

摘要翻译： 提供了一种方法和系统，用于处理用于命令用户界面执行功能的自然语言用户查询。 单个用户查询根据功能的类型分类，并且多个用户查询可以与定义特定命令有关。 为了帮助分类，确定每个用户查询的查询类型，其中查询类型是请求特定新命令执行特定类型的功能的功能查询之一，与特定新命令相关联的实体相关的实体查询 具有特定类型的功能和响应于澄清问题的澄清查询，以澄清具有特定类型功能的先前用户查询。 可以使用多种自然语言处理技术来处理功能查询，并且从组合的每种技术的分数来确定哪种类型的功能被命令。

公开(公告)号：US08329568B1

公开(公告)日：2012-12-11

申请号：US12772969

申请日：2010-05-03

申请人： Jae-Gyung Ahn ,  Myongseob Kim ,  Ping-Chin Yeh ,  Zhiyuan Wu ,  John Cooksey

发明人： Jae-Gyung Ahn ,  Myongseob Kim ,  Ping-Chin Yeh ,  Zhiyuan Wu ,  John Cooksey

IPC分类号： H01L21/425

CPC分类号： H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.

摘要翻译： 在本发明的一个实施例中，提供了场效应晶体管器件。 场效应晶体管器件包括有源区，包括第一导电类型的第一半导体材料。 通道区域包括在有效区域内。 栅极区域覆盖沟道区域，并且第一源极/漏极区域和第二源极/漏极区域被嵌入有源区域中并且被沟道区域彼此间隔开。 第一源极/漏极区域和第二源极/漏极区域各自包括与第一导电类型相反的第二导电类型的第二半导体材料。 阱区域嵌入有源区域中，并且通过沟道区域和第二源极/漏极区域与第一源极/漏极区域间隔开。 阱抽头区域包括第一导电类型的第二半导体材料。 第一源极/漏极区域和第二源极/漏极区域以及阱阱区域是外延沉积物。

公开(公告)号：US10387410B2

公开(公告)日：2019-08-20

申请号：US14233640

申请日：2012-07-19

申请人： Kaheer Suleman ,  Joshua R. Pantony ,  Wilson Hsu ,  Zhiyuan Wu ,  Phil Tregenza ,  Sam Pasupalak

发明人： Kaheer Suleman ,  Joshua R. Pantony ,  Wilson Hsu ,  Zhiyuan Wu ,  Phil Tregenza ,  Sam Pasupalak

IPC分类号： G06F16/245 ,  G06F16/28 ,  G06F3/16 ,  G06F17/28 ,  G06Q30/06 ,  G10L15/18

摘要： A method and system are provided for processing natural language user queries for commanding a user interface to perform functions. Individual user queries are classified in accordance with the types of functions and a plurality of user queries may be related to define a particular command. To assist with classification, a query type for each user query is determined where the query type is one of a functional query requesting a particular new command to perform a particular type of function, an entity query relating to an entity associated with the particular new command having the particular type of function and a clarification query responding to a clarification question posed to clarify a prior user query having the particular type of function. Functional queries may be processed using a plurality of natural language processing techniques and scores from each technique combined to determine which type of function is commanded.