公开(公告)号：US08450775B2

公开(公告)日：2013-05-28

申请号：US13229773

申请日：2011-09-12

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

IPC分类号： H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.

摘要翻译： 应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。 另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。

公开(公告)号：US07718500B2

公开(公告)日：2010-05-18

申请号：US11305584

申请日：2005-12-16

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

摘要翻译： 用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

公开(公告)号：US08017487B2

公开(公告)日：2011-09-13

申请号：US11399016

申请日：2006-04-05

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.

摘要翻译： 提出了应变通道晶体管结构和形成半导体器件的方法。 晶体管结构包括具有第一自然晶格常数的第一半导体材料的应变沟道区。 提供了覆盖应变通道区域的栅极电介质层，覆盖栅极电介质层的栅极电极和与应变通道区域相邻的源极区域和漏极区域。 源极区域和漏极区域中的一个或两个包括具有第二半导体材料的应力区域，其具有与第一自然晶格常数不同的第二自然晶格常数。 应激物区域具有掺杂剂杂质和/或应力诱导分子的渐变浓度。

公开(公告)号：US08288825B2

公开(公告)日：2012-10-16

申请号：US12780962

申请日：2010-05-17

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Judson Robert Holt

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： A structure and method for forming raised source/drain structures in a NFET device and embedded SiGe source/drains in a PFET device. We provide a NFET gate structure over a NFET region in a substrate and PFET gate structure over a PFET region. We provide NFET SDE regions adjacent to the NFET gate and provide PFET SDE regions adjacent to the PFET gate. We form recesses in the PFET region in the substrate adjacent to the PFET second spacers. We form a PFET embedded source/drain stressor in the recesses. We form a NFET S/D epitaxial Si layer over the NFET SDE regions and a PFET S/D epitaxial Si layer over PFET embedded source/drain stressor. The epitaxial Si layer over PFET embedded source/drain stressor is consumed in a subsequent salicide step to form a stable and low resistivity silicide over the PFET embedded source/drain stressor. We perform a NFET S/D implant by implanting N-type ions into NFET region adjacent to the NFET gate structure and into the NFET S/D stressor Si layer to form the raised NFET source/drains.

摘要翻译： 用于在NFET器件中形成凸起的源极/漏极结构并在PFET器件中形成嵌入的SiGe源极/漏极的结构和方法。 我们在衬底上的NFET区域和PFET区域上的PFET栅极结构提供NFET栅极结构。 我们提供与NFET栅极相邻的NFET SDE区域，并提供与PFET栅极相邻的PFET SDE区域。 我们在邻近PFET第二间隔物的衬底中的PFET区域中形成凹陷。 我们在凹槽中形成PFET嵌入式源极/漏极应力器。 我们在NFET SDE区域上形成NFET S / D外延Si层，并在PFET嵌入式源极/漏极应力器上形成PFET S / D外延Si层。 在随后的自对准硅化物步骤中，在PFET嵌入式源极/漏极应力源上的外延Si层被消耗，以在PFET嵌入式源极/漏极应力器上形成稳定和低电阻率的硅化物。 我们通过将N型离子注入到与NFET栅极结构相邻的NFET区域中并进入NFET S / D应力Si层来形成NFET S / D注入，以形成升高的NFET源极/漏极。

公开(公告)号：US07566609B2

公开(公告)日：2009-07-28

申请号：US11164568

申请日：2005-11-29

申请人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.

摘要翻译： 提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。 栅极结构包括栅极电介质层，导电层和绝缘层。 形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。 还提供了一种FET器件。

公开(公告)号：US20080283934A1

公开(公告)日：2008-11-20

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US20070293016A1

公开(公告)日：2007-12-20

申请号：US11424076

申请日：2006-06-14

申请人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

发明人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76218 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

摘要翻译： 半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。 半导体结构还包括位于掺杂区和外延区的最后隔离区。 最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。 制造半导体结构的方法提供了在外延区之前形成掺杂区。 掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。 具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

公开(公告)号：US08912567B2

公开(公告)日：2014-12-16

申请号：US12852995

申请日：2010-08-09

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

摘要翻译： 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US20080286916A1

公开(公告)日：2008-11-20

申请号：US12179042

申请日：2008-07-24

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Brian L. Tessier

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Brian L. Tessier

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845

摘要： Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric.

摘要翻译： 公开了用替换的栅极和相关结构来施加晶体管的沟道的方法。 一种方法可以包括在包括其栅极的晶体管上提供固有应力的材料; 在门上移除一部分本征应力材料; 去除栅极的至少一部分，允许由栅极保持的应力传递到通道; 用更换的门更换（或补充）门; 并去除本征应力材料。 拆卸和更换门允许原始闸门保持的应力传递到通道，替换闸门保持（记住）这种情况。 这些方法不会损坏栅极电介质。

公开(公告)号：US20080116482A1

公开(公告)日：2008-05-22

申请号：US11561982

申请日：2006-11-21

申请人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

发明人： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

IPC分类号： H01L27/092 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78639

摘要： Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

摘要翻译： 通过在源极/漏极区域或沟道区域之下形成应力区域并且在应力区域上使用横向外延形成选择性应变Si，从而在通道区域上具有应力的FET器件的实施例。 在第一示例性实施例中，在FET的沟道区之下的应力区域上形成横向外延层。 在第二示例性实施例中，在FET的源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在第三示例性实施例中，形成PFET和NFET器件。 在PFET器件中，在源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在NFET器件中，横向外延层形成在NFET的沟道区下方的应力区域上。