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    Method and apparatus for extracting line segments from an image of an object
    2.
    发明授权
    Method and apparatus for extracting line segments from an image of an object 失效
    从对象的图像中提取线段的方法和装置

    公开(公告)号：US5422962A

    公开(公告)日：1995-06-06

    申请号：US32312

    申请日：1993-03-17

    申请人： Yusuke Yasukawa ,  Fumi Hasegawa ,  Yasushi Inamoto ,  Susumu Kawakami

    发明人： Yusuke Yasukawa ,  Fumi Hasegawa ,  Yasushi Inamoto ,  Susumu Kawakami

    IPC分类号： G06K9/46 ,  G06K9/32 ,  G06K9/36

    CPC分类号： G06K9/4647

    摘要： A method of extracting a line segment contained in an original image includes the steps of clipping an image, which conforms to the size of a receptive field defining a small area, from the original image, projecting the clipped receptive-field image from a predetermined projection direction onto an axis (.rho. axis) that intersects the projection direction to obtain projection values at positions along the .rho. axis, subjecting the projection values to differentiation processing along the .rho. axis, similarly subjecting projection values, which are obtained by successively varying a projection-direction angle .theta. incrementally a predetermined amount, to differentiation processing along the .rho. axis to thereby obtain a differential value at each position on a .rho.-.theta. plane, and extracting a line segment contained in the receptive-field image based upon a peak position (.rho.,.theta.) of the differential values.

    摘要翻译： 提取包含在原始图像中的线段的方法包括以下步骤：从原始图像中剪切符合限定小区域的接收域的大小的图像，从预定投影中投影剪辑的接收场图像 方向到与投影方向相交的轴（rho轴），以在沿着rho轴的位置处获得投影值，对投影值进行沿着rho轴的微分处理，类似地，通过连续改变投影值， 方向角θ渐变为预定量，沿着rho轴进行微分处理，从而在rho-θ平面上的每个位置处获得差分值，并且基于峰位置（rho）提取包含在接受场图像中的线段 ，theta）的差分值。

    Data access control system and computer-readable medium storing data access control program
    5.
    发明授权
    Data access control system and computer-readable medium storing data access control program 失效
    数据访问控制系统和存储数据访问控制程序的计算机可读介质

    公开(公告)号：US6049891A

    公开(公告)日：2000-04-11

    申请号：US40994

    申请日：1998-03-19

    申请人： Yasushi Inamoto

    发明人： Yasushi Inamoto

    IPC分类号： G06F3/06 ,  G06F11/00 ,  G06F11/14 ,  G06F13/14

    CPC分类号： G06F11/1435 ,  G06F11/00 ,  Y10S707/99943

    摘要： A data access control system for reading/writing data from/to an array of storage units, which is resilient to read/writing errors to avoid lost data, while meeting the realtime requirements. Consecutive data blocks are stored in a plurality of storage units in a distributed manner by using a striping technique. A time slot vacancy monitor checks the present activities of the storage units to find a vacant time slot during which no data read/write operations are scheduled. A data read/write controller finds a particular data block that is scheduled to be read out of/written the storage units just after the vacant time slot has expired. When such a data block is found, the data read/write controller prefetches that data block during the vacant time slot. If a read/write error is encountered during the prefetch of the data block, the data read/write controller attempts read/write retry operations in the remaining period of the vacant time slot until the scheduled data output time comes. This read/write retry operation will be repeated, if necessary, within the limited time period.

    摘要翻译： 一种用于从/存储单元阵列读取/写入数据的数据访问控制系统，其可满足读/写错误以避免丢失的数据，同时满足实时要求。 连续数据块通过使用条带化技术以分布式存储在多个存储单元中。 时隙空缺监视器检查存储单元的当前活动以找到空闲的时隙，在该空闲时隙期间不计划数据读/写操作。 数据读/写控制器发现在空闲时隙到期之后被调度为读/写存储单元的特定数据块。 当发现这样的数据块时，数据读/写控制器在空闲时隙期间预取该数据块。 如果在数据块的预取期间遇到读/写错误，则数据读/写控制器在空闲时隙的剩余时间段内尝试读/写重试操作，直到调度的数据输出时间到来。 如有必要，将在有限的时间内重复此读/写重试操作。

    Storage device control system with an internal bus wherein a network interface has a data line for memory transfer
    6.
    发明授权
    Storage device control system with an internal bus wherein a network interface has a data line for memory transfer 失效
    具有内部总线的存储设备控制系统，其中网络接口具有用于存储器传送的数据线

    公开(公告)号：US5737634A

    公开(公告)日：1998-04-07

    申请号：US554695

    申请日：1995-11-07

    申请人： Takashi Hamano ,  Tsutomu Togo ,  Hiroichi Egawa ,  Yasushi Inamoto ,  Kiichi Matsuda

    发明人： Takashi Hamano ,  Tsutomu Togo ,  Hiroichi Egawa ,  Yasushi Inamoto ,  Kiichi Matsuda

    IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F13/12 ,  G06F13/36 ,  G06F13/14

    CPC分类号： G06F13/128

    摘要： A CPU, a main memory, a network interface section and a control section are connected to an internal bus. The control section is connected to a storage device to control read-out and write-in processes relative to the storage device. The network interface section receives an access request to the storage device transferred through a network and sends it to the control section through the CPU. The network interface section and the control section are connected to each other by an exclusive line. Data read out of the storage device and data to be written into it is transferred through the exclusive line.

    摘要翻译： CPU，主存储器，网络接口部分和控制部分连接到内部总线。 控制部连接到存储装置，以控制相对于存储装置的读出和写入处理。 网络接口部分接收到通过网络传送的存储设备的访问请求，并通过CPU将其发送到控制部分。 网络接口部分和控制部分通过专用线彼此连接。 从存储设备读出的数据和要写入的数据通过专用线传输。

    Multimedia server having a plurality of stream controllers directly connected to the network
    7.
    发明授权
    Multimedia server having a plurality of stream controllers directly connected to the network 失效
    具有直接连接到网络的多个流控制器的多媒体服务器

    公开(公告)号：US5717854A

    公开(公告)日：1998-02-10

    申请号：US563544

    申请日：1995-11-28

    申请人： Hiroichi Egawa ,  Kiichi Matsuda ,  Yasushi Inamoto ,  Takashi Hamano ,  Naoshi Matsuo

    发明人： Hiroichi Egawa ,  Kiichi Matsuda ,  Yasushi Inamoto ,  Takashi Hamano ,  Naoshi Matsuo

    IPC分类号： G06F13/00 ,  G06F15/16 ,  G06F15/173 ,  G06F17/30 ,  H04N7/14 ,  H04N7/173 ,  H04Q11/04

    CPC分类号： H04L49/105 ,  H04L49/3081 ,  H04N7/147 ,  H04N7/17336 ,  H04Q11/0478 ,  H04L2012/5638

    摘要： Each of processor units 31-1-31-n comprises a CPU, memory, and interface function. A high-speed communications network 32 interconnects the processor units for inter-processor communications. Each of input/output units 33-1-33-n stores multimedia data and transmits the multimedia data through the network under the control of the corresponding processor unit. A processor control unit 34 controls the process of each of the processor units 31-1-31-n according to the process request received through the network. A switch 35 connects each of the input/output units 33-1-33-n to the network and exchanges data through the network. A communications line 36 transfers an instruction, etc. from the processor control unit 34 to each of the processor units 31-1-31-n.

    摘要翻译： 每个处理器单元31-1-31-n包括CPU，存储器和接口功能。 高速通信网络32将用于处理器间通信的处理器单元互连。 输入/输出单元33-1-33-n中的每一个存储多媒体数据，并在对应的处理器单元的控制下通过网络发送多媒体数据。 处理器控制单元34根据通过网络接收的处理请求来控制每个处理器单元31-1-31-n的处理。 开关35将输入/输出单元33-1-33-n中的每一个连接到网络并通过网络交换数据。 通信线路36将处理器控制单元34的指令等传送到每个处理器单元31-1-31-n。

    Data transfer control device and method for switching memory regions between storage devices when accessing is halted
    8.
    发明授权
    Data transfer control device and method for switching memory regions between storage devices when accessing is halted 失效
    数据传输控制装置和方法，用于在访问时切换存储设备之间的存储区域

    公开(公告)号：US5918000A

    公开(公告)日：1999-06-29

    申请号：US539774

    申请日：1995-10-05

    申请人： Hiroaki Yamashita ,  Yasushi Inamoto ,  Kiichi Matsuda

    发明人： Hiroaki Yamashita ,  Yasushi Inamoto ,  Kiichi Matsuda

    IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F11/20 ,  G06F13/36 ,  G11B20/12 ,  G11B20/18 ,  G06F11/08

    CPC分类号： G06F11/2094 ,  G06F3/0625 ,  G06F3/0658 ,  G06F3/0689 ,  G11B20/1252 ,  G11B20/1833 ,  G11B20/1883 ,  G11B2220/20 ,  Y02B60/1246

    摘要： A data transfer control device and controlling method in which data on a storage medium is read continuously. The data transfer control device includes M storage units each for storing respectively at least two kinds of different data among N kinds of data in memory regions, a transmission control element for transmitting the N kinds of data and a spare storage unit for storing at least one kind of data among said N kinds of data. The transfer control device includes a judging element for judging whether accessing any one of the M storage units must be halted. Switching element for switching a memory region to the spare storage unit and the remaining (M-1) storage unit when the judging element judges that accessing must be halted and then the switching element performs an accessing operation. The data transfer control device can suppress an increase in the device forming cost, power consumption, and installation area, and can increase the amount of data which can be stored according to the number of storage units installed.

    摘要翻译： 一种数据传送控制装置及其中持续读取存储介质上的数据的控制方法。 数据传送控制装置包括M个存储单元，每个存储单元分别存储存储区域中的N种数据中的至少两种不同数据，用于发送N种数据的传输控制元件和用于存储至少一个 所述N种数据中的数据种类。 传送控制装置包括用于判断是否必须停止访问M个存储单元中的任何一个的判断元件。 当判断元件判定该访问必须停止，然后开关元件执行访问操作时，用于将存储器区域切换到备用存储单元和剩余（M-1）个存储单元。 数据传输控制装置可以抑制装置成本成本，功耗和安装面积的增加，并且可以根据安装的存储单元的数量增加可以存储的数据量。

    Method and device for obtaining sum of products using integrated circuit
    9.
    发明授权
    Method and device for obtaining sum of products using integrated circuit 失效
    使用集成电路获得产品总和的方法和装置

    公开(公告)号：US5138574A

    公开(公告)日：1992-08-11

    申请号：US746816

    申请日：1991-08-15

    申请人： Takashi Aoki ,  Yasushi Inamoto

    发明人： Takashi Aoki ,  Yasushi Inamoto

    IPC分类号： G06F17/10 ,  G06F7/50 ,  G06F7/52 ,  G06F7/544

    CPC分类号： G06F7/5324 ,  G06F7/5338 ,  G06F7/5443 ,  G06F2207/3884

    摘要： A method and a device for obtaining a sum of products which are applied to a spatial filter in a picture processing system, a transversal equalizer in radio communication equipment or the like, are based on the division of a portion of or entire operand by a predetermined figure length. The sum of products is first calculated among the operands having the same figure position, and the obtained results are added while shifting the figure in response to the divided figure length and the figure position. The lower figures, which do not need to be added, are then appended under the lowest figure of the addition result as is. Thus, the scale of the figure processed in an integrated circuit (IC) is decreased and the application of an IC of identical rating is further promoted.

    摘要翻译： 一种用于获得应用于图像处理系统中的空间滤波器，无线电通信设备等中的横向均衡器的乘积之和的方法和装置，基于将一部分或全部操作数除以预定的 图长。 首先在具有相同图形位置的操作数之间计算乘积之和，并且响应于分割图形长度和图形位置移动图形而添加所获得的结果。 然后，不需要添加的较低的数字被附加在加法结果的最低数字下。 因此，在集成电路（IC）中处理的图形的尺度减小，并且进一步促进了具有相同等级的IC的应用。