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    Field effect transistor formed on an insulating substrate and integrated circuit thereof
    2.
    发明授权
    Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权

    公开(公告)号：US08450799B2

    公开(公告)日：2013-05-28

    申请号：US11975923

    申请日：2007-10-22

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

    IPC分类号： H01L29/34

    CPC分类号： H01L29/78615 ,  H01L29/66772

    摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

    Memory cell array
    3.
    发明授权
    Memory cell array 有权
    存储单元阵列

    公开(公告)号：US08094484B2

    公开(公告)日：2012-01-10

    申请号：US12644851

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C11/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取 放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和 门极阈值电压以下。

    MEMORY DEVICE AND READING METHOD THEREOF
    4.
    发明申请
    MEMORY DEVICE AND READING METHOD THEREOF 有权
    存储器件及其读取方法

    公开(公告)号：US20100208522A1

    公开(公告)日：2010-08-19

    申请号：US12601788

    申请日：2008-05-23

    申请人： Yutaka Hayashi ,  Kazuhika Matsumoto ,  Takafumi Kamimura

    发明人： Yutaka Hayashi ,  Kazuhika Matsumoto ,  Takafumi Kamimura

    IPC分类号： G11C16/02 ,  H01L27/105

    CPC分类号： H01L29/7881 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/0657 ,  H01L29/1606 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/6684 ,  H01L29/7781 ,  H01L29/792

    摘要： A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.

    摘要翻译： 存储器件（1）至少包括具有由第一表面包围的长度，第一表面和横截面的第一半导体区域（100），设置在第一表面上的存储器件（300）和栅极 400），并且将第一半导体区域（100）的横截面的等效截面半径设定为等于或小于存储装置（300）的等效氧化硅膜厚度， 实现低编程电压。 横截面的等效截面半径r设定为10nm以下，栅极长度设定为20nm以下，使得转换为栅极电压的多级间隔成为能够在室内识别的特定值 温度。

    Memory Cell Array
    5.
    发明申请
    Memory Cell Array 有权
    存储单元阵列

    公开(公告)号：US20100165696A1

    公开(公告)日：2010-07-01

    申请号：US12644608

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C5/06 ,  G11C7/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线 以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线 或更少。

    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof
    6.
    发明授权
    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof 有权
    高电压工作场效应晶体管，其偏置电路及其高电压电路

    公开(公告)号：US07545018B2

    公开(公告)日：2009-06-09

    申请号：US11063388

    申请日：2005-02-22

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

    摘要： A high voltage operating field effect transistor has a substrate, a source region and a drain region which are spaced apart from each other in a surface of the substrate, a semiconductor channel formation region disposed in the surface of the substrate between the source region and the drain region, a gate region disposed above the channel formation region, and a gate insulating film region disposed between the channel formation region and the gate region. At least one of a signal electric potential and a signal current is supplied to the source region, and a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential is supplied to the gate region. One end of a rectifying device is connected to the gate region, and a second constant electric potential is supplied to the other end of the rectifying device.

    摘要翻译： 高电压工作场效应晶体管具有在基板的表面上彼此间隔开的基板，源极区域和漏极区域，设置在基板的表面中的源极区域与源极区域之间的半导体沟道形成区域， 漏极区域，设置在沟道形成区域上方的栅极区域和设置在沟道形成区域和栅极区域之间的栅极绝缘膜区域。 将信号电位和信号电流中的至少一个提供给源极区域，并且具有绝对值等于或大于根据漏极电流的增减的第一恒定电位变化的偏置电位 电位被提供给栅极区域。 整流装置的一端与栅极区域连接，第二恒定电位被提供给整流装置的另一端。

    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof
    7.
    发明申请
    High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof 有权
    高电压工作场效应晶体管，其偏置电路及其高电压电路

    公开(公告)号：US20090014765A1

    公开(公告)日：2009-01-15

    申请号：US12283639

    申请日：2008-09-12

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

    IPC分类号： H03K5/08 ,  H01L27/06

    CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

    摘要： A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

    摘要翻译： 高电压工作场效应晶体管具有在衬底的表面中彼此间隔开的源极区和漏极区。 源区域可操作以接收信号电位和信号电流中的至少一个。 半导体沟道形成区域设置在源极区域和漏极区域之间的衬底的表面中。 栅极区域设置在沟道形成区域上方，并且可操作以接收具有等于或大于根据漏极电位的增加或减小而改变的第一恒定电位的绝对值的偏置电位。 栅极绝缘膜区域设置在沟道形成区域和栅极区域之间。

    Field effect transistor formed on an insulating substrate and integrated circuit thereof
    8.
    发明授权
    Field effect transistor formed on an insulating substrate and integrated circuit thereof 有权
    形成在绝缘基板上的场效应晶体管及其集成电路

    公开(公告)号：US07282763B2

    公开(公告)日：2007-10-16

    申请号：US10228847

    申请日：2002-08-27

    申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

    发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

    IPC分类号： H01L29/94

    CPC分类号： H01L29/78615 ,  H01L29/42384 ,  H01L29/78645

    摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film formed on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor thin film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. A conductive thin film is connected with the second region and the third region. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation and without application of a fixed bias potential to the third region.

    摘要翻译： 场效应晶体管具有绝缘基板，形成在绝缘基板上的半导体薄膜和形成在半导体薄膜上的栅极绝缘膜。 在栅极绝缘膜上形成第一栅电极。 在第一栅电极的长度方向的相对侧的半导体薄膜的表面上或表面上形成具有第一导电类型的第一区域和第二区域。 具有与第一导电类型相反的第二导电类型的第三区域与第一栅电极的宽度方向上的第二区域并排设置在半导体膜上或半导体膜中。 导电薄膜与第二区域和第三区域连接。 第二栅电极沿着第二区形成在栅极绝缘膜上。 具有第一导电类型的第四区域形成在第二区域的相对于第二栅电极的相反侧上或半导体膜中。 根据电路操作将第一和第四区域中的一个用作输出区域，并且不向第三区域施加固定的偏置电位。

    Bearing device for wheel
    9.
    发明申请
    Bearing device for wheel 有权
    车轮轴承装置

    公开(公告)号：US20060133706A1

    公开(公告)日：2006-06-22

    申请号：US10559271

    申请日：2004-06-01

    申请人： Koichi Okada ,  Yutaka Hayashi ,  Kenichi Iwamoto ,  Takashi Koike

    发明人： Koichi Okada ,  Yutaka Hayashi ,  Kenichi Iwamoto ,  Takashi Koike

    IPC分类号： F16C41/04

    CPC分类号： F16C19/186 ,  F16C19/52 ,  F16C25/08 ,  F16C41/00

    摘要： According to the present invention, there is provided a bearing apparatus for a wheel of vehicle comprising a hub wheel integrally formed therewith a wheel mounting flange on the periphery at one end thereof, and a double row rolling bearing, the double row rolling bearing comprising an outer member integrally formed therewith a body mounting flange on the periphery thereof and also formed therewith double row outer raceway surfaces, an inner member including said hub wheel and formed therewith double row inner raceway surfaces each arranged opposite to each of said double row outer surfaces, and double row rolling elements freely rotatably contained between said double row outer and second raceway surfaces, said double row rolling bearing being adapted to be applied a predetermined preload characterized in that: there are arranged a separate outer or inner ring on at least one of said outer and inner members, and a preload varying means arranged at an abutting portion between said outer and inner members for varying the preload applied to the bearing, said preload varying means can be extended or contracted based on an output signal from a detecting sensor for detecting the running condition of vehicle.

    摘要翻译： 根据本发明，提供了一种用于车轮的轴承装置，其包括：轮毂轮，其一端形成有轮安装凸缘，其一端在其外周;以及双列滚动轴承，所述双列滚动轴承包括： 外部构件与其周边一体地形成有本体安装凸缘，并且还具有双列外滚道表面，内部构件包括所述轮毂轮，并且形成有与每个所述双列外表面相对布置的双列内滚道表面， 以及可自由旋转地容纳在所述双列外滚道表面和第二滚道表面之间的双列滚动元件，所述双列滚动轴承适于施加预定的预载荷，其特征在于：在所述双列滚动轴承中的至少一个上设置有单独的外圈或内圈 外部和内部构件，以及布置在所述出口之间的邻接部分处的预加载变化装置 以及用于改变施加到轴承的预载荷的内部构件，所述预压变化装置可以基于来自用于检测车辆行驶状态的检测传感器的输出信号而被伸缩。

    Ceramic sintered product and process for producing the same
    10.
    再颁专利
    Ceramic sintered product and process for producing the same 有权
    陶瓷烧结产品及其制造方法

    公开(公告)号：USRE39120E1

    公开(公告)日：2006-06-06

    申请号：US10124067

    申请日：2002-04-16

    申请人： Yoshihisa Sechi ,  Masahiro Sato ,  Hiroshi Aida ,  Shoji Kohsaka ,  Yutaka Hayashi

    发明人： Yoshihisa Sechi ,  Masahiro Sato ,  Hiroshi Aida ,  Shoji Kohsaka ,  Yutaka Hayashi

    IPC分类号： C04B35/195

    CPC分类号： H01L23/15 ,  C04B35/195 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Low thermal expansion ceramics contains a cordierite crystal phase, wherein a phase of a crystalline compound containing at least one element selected from the group consisting of an alkaline earth element other than Mg, a rare earth element, Ga and In, is precipitated in the grain boundaries of said crystal phase, said ceramics has a relative density of not smaller than 95%, a coefficient of thermal expansion of not larger than 1×10−6/° C. at 10 to 40° C., and a Young's modulus of not smaller than 130 GPa. That is, the ceramics has a small coefficient of thermal expansion, is deformed very little depending upon a change in the temperature, has a very high Young's modulus and is highly rigid and is resistance against external force such as vibration. Accordingly, the ceramics is very useful as a member for supporting a wafer or an optical system is a lithography apparatus that forms high resolution circuit patterns on a silicon wafer.

    摘要翻译： 低热膨胀陶瓷含有堇青石结晶相，其中含有选自Mg以外的碱土金属元素，稀土元素，Ga和In中的至少一种元素的结晶化合物的相析出在晶粒中 所述晶相的边界，所述陶瓷的相对密度不低于95％，热膨胀系数在10-40℃下不大于1×10 -6 /℃， 杨氏模量不小于130GPa。 也就是说，陶瓷具有小的热膨胀系数，根据温度的变化而变形很小，具有非常高的杨氏模量，并且是高度刚性的并且是抗外力如振动的抵抗力。 因此，陶瓷作为用于支撑晶片的部件是非常有用的，或者光学系统是在硅晶片上形成高分辨率电路图案的光刻设备。