公开(公告)号：US08760926B2

公开(公告)日：2014-06-24

申请号：US13534132

申请日：2012-06-27

申请人： Jun Osanai ,  Yoshitsugu Hirose ,  Kazuhiro Tsumura ,  Ayako Inoue

发明人： Jun Osanai ,  Yoshitsugu Hirose ,  Kazuhiro Tsumura ,  Ayako Inoue

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0441 ,  G11C16/26

摘要： Provided is a memory circuit in which erroneous writing is less likely to occur at the time of power-on. A memory circuit (10) includes: a P-channel non-volatile memory element (15) for writing, to which a voltage is applied between a source and a drain thereof only during writing so as to write data; and an N-channel non-volatile memory element (16) for reading, which has a control gate and a floating gate provided in common to a control gate and a floating gate of the P-channel non-volatile memory element (15) and to which a voltage is applied to a source and a drain thereof only during reading so as to read the data.

摘要翻译： 提供了在上电时不太可能发生错误写入的存储电路。 存储器电路（10）包括：用于写入的P沟道非易失性存储元件（15），仅在写入期间在其源极和漏极之间施加电压以便写入数据; 和用于读取的N沟道非易失性存储器元件（16），其具有与P沟道非易失性存储元件（15）的控制栅极和浮置栅极共同设置的控制栅极和浮置栅极，以及 仅在读取期间将电压施加到源极和漏极，以便读取数据。

公开(公告)号：US08012835B2

公开(公告)日：2011-09-06

申请号：US12283639

申请日：2008-09-12

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21/8234

CPC分类号： H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/78645 ,  H01L29/78654

摘要： A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

摘要翻译： 高电压工作场效应晶体管具有在衬底的表面中彼此间隔开的源极区和漏极区。 源区域可操作以接收信号电位和信号电流中的至少一个。 半导体沟道形成区域设置在源极区域和漏极区域之间的衬底的表面中。 栅极区域设置在沟道形成区域上方，并且可操作以接收具有等于或大于根据漏极电位的增加或减小而改变的第一恒定电位的绝对值的偏置电位。 栅极绝缘膜区域设置在沟道形成区域和栅极区域之间。

公开(公告)号：US07816212B2

公开(公告)日：2010-10-19

申请号：US12283638

申请日：2008-09-12

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Yoshifumi Yoshida ,  Jun Osanai

IPC分类号： H01L21/8234

CPC分类号： H01L29/4238

摘要： A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential.

摘要翻译： 高电压工作场效应晶体管具有衬底和设置在衬底的表面中的半导体沟道形成区域。 源极区域和漏极区域彼此间隔开，半导体沟道形成区域设置在源极区域和漏极区域之间。 栅极绝缘膜区域设置在半导体沟道形成区域上。 电阻栅极区域设置在栅极绝缘膜区域上。 源极电极设置在电阻栅极区域的源极区域侧并且可操作以接收信号电位。 漏极侧电极设置在电阻栅极区域的漏极侧，并且可操作以接收其绝对值等于或大于指定电位的绝对值的偏置电位，并且其根据增加或 降低漏极电位。

公开(公告)号：US07749880B2

公开(公告)日：2010-07-06

申请号：US11196095

申请日：2005-08-03

申请人： Jun Osanai

发明人： Jun Osanai

IPC分类号： H01L21/336 ,  H01L27/088

CPC分类号： H01L21/823468 ,  H01L21/3003 ,  H01L21/823412 ,  H01L27/0207

摘要： In a method of manufacturing a semiconductor integrated circuit device, a gate electrode is formed over a semiconductor substrate. An insulating film is then formed on the gate electrode and on regions corresponding to a source and a drain of the semiconductor integrated circuit device. The source and the drain are then formed. A nitride film is then selectively formed over the source and the gate electrode via the insulating film so that the nitride film extends over the gate electrode to a position short of a center of the gate electrode in a length direction thereof and so that a width of the nitride film is shorter than a channel width of the semiconductor integrated circuit device.

摘要翻译： 在制造半导体集成电路器件的方法中，在半导体衬底上形成栅电极。 然后在栅电极和对应于半导体集成电路器件的源极和漏极的区域上形成绝缘膜。 然后形成源极和漏极。 然后通过绝缘膜在源极和栅电极上选择性地形成氮化物膜，使得氮化物膜在栅电极上延伸到栅极电极的长度方向上的中心不到的位置， 氮化物膜比半导体集成电路器件的沟道宽度短。

公开(公告)号：US20100044765A1

公开(公告)日：2010-02-25

申请号：US12545431

申请日：2009-08-21

申请人： Shinjiro Kato ,  Jun Osanai

发明人： Shinjiro Kato ,  Jun Osanai

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： Provided is a metal oxide semiconductor (MOS) capacitor, in which trenches (3) are formed in a charge accumulation region (6) of a p-type silicon substrate (1) to reduce a contact area between the p-type silicon substrate (1) and a lightly doped n-type well region (2), thereby reducing a leak current from the lightly doped n-type well region (2) to the p-type silicon substrate (1).

摘要翻译： 提供一种金属氧化物半导体（MOS）电容器，其中沟槽（3）形成在p型硅衬底（1）的电荷累积区域（6）中，以减小p型硅衬底（1）的接触面积 1）和轻掺杂的n型阱区（2），从而减少从轻掺杂n型阱区（2）到p型硅衬底（1）的漏电流。

公开(公告)号：US20090101973A1

公开(公告)日：2009-04-23

申请号：US11975923

申请日：2007-10-22

申请人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

发明人： Yutaka Hayashi ,  Hisashi Hasegawa ,  Hiroaki Takasu ,  Jun Osanai

IPC分类号： H01L29/78

CPC分类号： H01L29/78615 ,  H01L29/66772

摘要： A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.

摘要翻译： 场效应晶体管具有绝缘基板，形成在绝缘基板上的半导体薄膜和半导体薄膜上的栅极绝缘膜。 在栅极绝缘膜上形成第一栅电极。 在第一栅电极的长度方向的相对侧的半导体膜的表面上或表面上形成具有第一导电类型的第一区域和第二区域。 具有与第一导电类型相反的第二导电类型的第三区域与第一栅电极的宽度方向上的第二区域并排设置在半导体膜上或半导体膜中。 第三区域和第二区域彼此接触并形成低电阻结。 第二栅电极沿着第二区形成在栅极绝缘膜上。 具有第一导电类型的第四区域形成在第二区域的相对于第二栅电极的相反侧上或半导体膜中。 根据电路操作将第一和第四区域中的一个用作输出区域。

公开(公告)号：US20080185639A1

公开(公告)日：2008-08-07

申请号：US12027655

申请日：2008-02-07

申请人： Tomomitsu Risaki ,  Jun Osanai

发明人： Tomomitsu Risaki ,  Jun Osanai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/785

摘要： Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increase the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

摘要翻译： 沟槽部分（10）形成在井（5）中，以便在井（5）中提供不均匀性。 在沟槽部分（10）的上表面和内部经由绝缘膜（7）形成栅电极（2）。 源极区域（3）以栅极长度方向形成在栅电极（2）的一侧，而另一侧的漏极区域（4）形成。 源极区域（3）和漏极区域（4）都形成为靠近栅电极（2）的底部附近。 通过深深地形成源极区域（3）和漏极区域（4），电流均匀地流过整个沟槽部分（10），并且在阱（5）中形成的凹凸增加了有效栅极宽度以降低导通电阻 并提高其驱动能力。

公开(公告)号：US20050190628A1

公开(公告)日：2005-09-01

申请号：US11066033

申请日：2005-02-25

申请人： Jun Osanai

发明人： Jun Osanai

IPC分类号： H01L29/417 ,  G11C5/00 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823475 ,  H01L21/823412 ,  H01L21/823418

摘要： In a semiconductor integrated circuit device according to the present invention, source wiring metal is allowed to overlap a gate electrode of the MOS transistor, and an overlap amount in which the wiring metal overlaps the gate electrode in a channel width direction is made variable according to a pattern designing value, enabling multi-Vth integrated circuit without increasing the number of manufacturing steps.

摘要翻译： 在根据本发明的半导体集成电路器件中，允许源极布线金属与MOS晶体管的栅极重叠，并且根据沟道宽度方向将布线金属与栅电极重叠的重叠量根据 模式设计值，实现多Vth集成电路，而不增加制造步骤数量。

公开(公告)号：US06921949B2

公开(公告)日：2005-07-26

申请号：US10609957

申请日：2003-06-30

申请人： Hirofumi Harada ,  Jun Osanai

发明人： Hirofumi Harada ,  Jun Osanai

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  G01R19/00

CPC分类号： H01L29/4933 ,  H01L27/092 ,  H01L29/7833

摘要： A semiconductor integrated circuit device is comprised of an amplifier circuit having first and second PMOS and NMOS transistors. The first PMOS transistor has a gate electrode and a drain electrode connected together. The second PMOS transistor has a gate electrode connected to the gate electrode of the first PMOS transistor and a course electrode connected to a course electrode of the first PMOS transistor. The first NMOS transistor has a drain electrode connected to the drain electrode of the first PMOS transistor and a gate electrode sat as a first input terminal. The second NMOS transistor has a drain electrode connected to a drain electrode of the second PMOS transistor, a source electrode connected to a sourse electrode of the first NMOS transistor, and a gate electrode sat as a second input terminal. At least one of the first NMOS transistor and the second NMOS transistor is comprised of a buried channel transistor.

摘要翻译： 半导体集成电路器件包括具有第一和第二PMOS和NMOS晶体管的放大器电路。 第一PMOS晶体管具有连接在一起的栅电极和漏电极。 第二PMOS晶体管具有连接到第一PMOS晶体管的栅电极的栅电极和连接到第一PMOS晶体管的线圈电极的电极电极。 第一NMOS晶体管具有连接到第一PMOS晶体管的漏电极的漏电极和作为第一输入端子的栅极电极。 第二NMOS晶体管具有连接到第二PMOS晶体管的漏电极的漏电极，连接到第一NMOS晶体管的源电极的源电极和作为第二输入端子的栅电极。 第一NMOS晶体管和第二NMOS晶体管中的至少一个由掩埋沟道晶体管构成。

公开(公告)号：US20050074929A1

公开(公告)日：2005-04-07

申请号：US10398035

申请日：2002-06-18

申请人： Hisashi Hasegawa ,  Jun Osanai

发明人： Hisashi Hasegawa ,  Jun Osanai

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L28/20 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629

摘要： There is provided a manufacturing method using a structure capable of realizing a power management semiconductor device and an analog semiconductor device, in which low costs, short manufacturing periods, and low voltage operation are possible, which have low power consumption, high drive power, high grade function, and high accuracy. With respect to the power management semiconductor device and the analog semiconductor device which each include a CMOS transistor and a resistor, the manufacturing method is a method of obtaining a P-type polycide structure as a laminate structure of a P-type polycrystalline silicon film and a high melting point metallic silicide film for respective gate electrodes of an NMOS transistor and a PMOS transistor as divided by a conductivity type thereof in a CMOS transistor. In addition, a resistor used for a voltage dividing circuit and a CR circuit is formed by using a polycrystalline silicon film as a layer different from the gate electrode.

摘要翻译： 提供了一种使用能够实现功率管理半导体器件和模拟半导体器件的结构的制造方法，其中低成本，低制造周期和低电压操作是可能的，其具有低功耗，高驱动功率，高 等级功能，精度高。 对于各自包括CMOS晶体管和电阻器的电源管理半导体器件和模拟半导体器件，制造方法是获得P型多晶硅结构作为P型多晶硅膜和 用于CMOS晶体管和PMOS晶体管的各个栅电极的高熔点金属硅化物膜，其在CMOS晶体管中被其导电类型划分。 此外，通过使用多晶硅膜作为与栅电极不同的层，形成用于分压电路和CR电路的电阻器。