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    ATM switching system
    1.
    发明授权
    ATM switching system 失效
    ATM交换系统

    公开(公告)号：US4956839A

    公开(公告)日：1990-09-11

    申请号：US382419

    申请日：1989-07-20

    申请人： Yutaka Torii ,  Makoto Mori ,  Shinobu Gohara ,  Kenichi Ohtsuki ,  Yoshito Sakurai

    发明人： Yutaka Torii ,  Makoto Mori ,  Shinobu Gohara ,  Kenichi Ohtsuki ,  Yoshito Sakurai

    IPC分类号： H04L12/70 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  H04L12/937

    CPC分类号： H04L49/309 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/503 ,  H04L2012/5636 ,  H04L2012/5674 ,  H04L49/1507 ,  H04L49/254 ,  Y10S370/905

    摘要： In the ATM switching system, an ATM speech path is divided into a plurality of functional blocks. A routing function for distributing cells (packets) each of a fixed length to addresses outgoing lines and a logical multiplexing function are imparted to a switch, while other functions associated with a line typified by a phase synchronizing function and a flow control function are incorporated en bloc in ATM line terminating units and functions capable of being processed by hardware in common to the lines are assembled in a line common unit. The ATM line terminating unit physically terminates transmission lines and performs the processing relevant to header information of the cells each of a fixed length (ATM terminating processing) and includes a cell phase synchronizing circuit for matching the temporal positions of the cells among the lines and a flow control circuit for avoiding overload exceeding the load declared by subscriber terminal. The line common unit serves for processings of call control signals and the calls and includes a signal processing circuit and a control circuit. The switch performs cell multiplexing and switching and is constituted by a self-routing switch.

    ATM cell switching system
    4.
    发明授权
    ATM cell switching system 失效
    ATM信元交换系统

    公开(公告)号：US06728242B2

    公开(公告)日：2004-04-27

    申请号：US10374998

    申请日：2003-02-28

    申请人： Yoshito Sakurai ,  Kenichi Ohtsuki ,  Shinobu Gohara ,  Makoto Mori ,  Akira Horiki ,  Takao Kato ,  Hiroshi Kuwahara

    发明人： Yoshito Sakurai ,  Kenichi Ohtsuki ,  Shinobu Gohara ,  Makoto Mori ,  Akira Horiki ,  Takao Kato ,  Hiroshi Kuwahara

    IPC分类号： H04L1256

    CPC分类号： H04L12/5601 ,  H04J3/247 ,  H04L12/5602 ,  H04L45/04 ,  H04L49/108 ,  H04L49/203 ,  H04L49/255 ,  H04L49/256 ,  H04L49/3081 ,  H04L2012/5627 ,  H04L2012/5631 ,  H04L2012/5638 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682 ,  H04Q11/0478

    摘要： An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

    摘要翻译： ATM交换系统包括具有多个输入端口和具有相同信元传输速率的多个输出端口的开关单元，以及多路复用器，用于将从至少两个输出端口输出的单元列复用为单个单元列，并输出该单元 训练到高速输出线（和/或解复用器，用于从输出端口多路复用到多个单元列，并将单元列输出到多个低速输出线）。 开关单元包括缓冲存储器，用于临时存储从输入端口输入的单元，同时形成用于每个单元将被输出到的每个输出线的队列链;解复用器，用于将从缓冲存储器读取的单元在输出端口之中分配 以及缓冲存储器控制电路，用于通过共享缓冲存储器来控制单元的写入和读取操作。 缓冲存储器控制电路具有用于输出要从共享缓冲存储器读取的单元被输出的输出行的标识符的控制表装置，并且从由控制器输出的输出行标识符指定的链中读取单元 表装置。