公开(公告)号：US08339183B2

公开(公告)日：2012-12-25

申请号：US12509367

申请日：2009-07-24

申请人： Khin Htoo ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Yuxin Wang

发明人： Khin Htoo ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Yuxin Wang

IPC分类号： G05F1/10

CPC分类号： H02M3/073

摘要： A charge pump circuit for generating an output voltage is described. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler.

摘要翻译： 描述用于产生输出电压的电荷泵电路。 电荷泵电路通常具有两个分支。 当提供电荷泵电路的分支的时钟交替时，每个分支的输出将交替地提供输出电压，然后将其组合以形成泵输出。 这里描述的技术允许在两个分支之间传输电荷，使得当一个分支的电容器放电时，它用于对另一个分支中的电容器充电。 使用倍压型电路的示例性实施例，通过由单侧电压倍增器提供的时钟信号的升压版本，使用开关控制器实现分支之间的电荷转移。

公开(公告)号：US07889575B2

公开(公告)日：2011-02-15

申请号：US12235474

申请日：2008-09-22

申请人： Yuxin Wang ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Khin Htoo

发明人： Yuxin Wang ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Khin Htoo

IPC分类号： G11C5/14

CPC分类号： H03K17/145 ,  G11C5/143 ,  G11C7/04 ,  G11C2207/2254 ,  H03K2217/0018

摘要： Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.

摘要翻译： 提供了用于从接收的参考电压导出用于存储单元阵列的偏置电压的技术和相应的电路。 该电路包括电压确定电路，其连接以接收参考电压并从其产生偏置电压，温度感测电路和校准电路。 连接校准电路以接收偏置电压并从温度检测电路接收温度指示，并根据偏置电压和温度指示确定提供给电压确定电路的补偿因子，该电压确定电路基于 补偿因子。

公开(公告)号：US20110018617A1

公开(公告)日：2011-01-27

申请号：US12509367

申请日：2009-07-24

申请人： Khin Htoo ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Yuxin Wang

发明人： Khin Htoo ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Yuxin Wang

IPC分类号： G05F1/10

CPC分类号： H02M3/073

摘要： A charge pump circuit for generating an output voltage is described. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler

摘要翻译： 描述用于产生输出电压的电荷泵电路。 电荷泵电路通常具有两个分支。 当提供电荷泵电路的分支的时钟交替时，每个分支的输出将交替地提供输出电压，然后将其组合以形成泵输出。 这里描述的技术允许在两个分支之间传输电荷，使得当一个分支的电容器放电时，它用于对另一个分支中的电容器充电。 使用倍压型电路的示例性实施例，其中分支之间的电荷转移由使用开关控制器的升压版本的时钟信号完成，其由单侧电压倍增器

公开(公告)号：US20100073069A1

公开(公告)日：2010-03-25

申请号：US12235474

申请日：2008-09-22

申请人： Yuxin Wang ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Khin Htoo

发明人： Yuxin Wang ,  Feng Pan ,  Byungki Woo ,  Trung Pham ,  Khin Htoo

IPC分类号： H03K17/14

CPC分类号： H03K17/145 ,  G11C5/143 ,  G11C7/04 ,  G11C2207/2254 ,  H03K2217/0018

摘要： Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.

摘要翻译： 提供了用于从接收的参考电压导出用于存储单元阵列的偏置电压的技术和相应的电路。 该电路包括电压确定电路，其连接以接收参考电压并从其产生偏置电压，温度感测电路和校准电路。 连接校准电路以接收偏置电压并从温度检测电路接收温度指示，并根据偏置电压和温度指示确定提供给电压确定电路的补偿因子，该电压确定电路基于 补偿因子。

公开(公告)号：US20100157681A1

公开(公告)日：2010-06-24

申请号：US12715858

申请日：2010-03-02

申请人： Feng Pan ,  Trung Pham ,  Byungki Woo

发明人： Feng Pan ,  Trung Pham ,  Byungki Woo

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C16/30

摘要： A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.

摘要翻译： 非易失性存储器件具有要并行感测的存储器单元的单独页面。 存储器件包括源极电平跟踪电路，其被耦合以从字线电压源接收预定字线电压，并且在一个或多个页面的聚合源节点处接收电压电平，并被耦合以向存储器的字线提供输出电压 在感测操作期间，源电平跟踪电路包括运算放大器，由此输出电压是字线电压偏移量，以跟踪聚集节点处的电压电平，并补偿源极偏移误差，这是由于在 接地回路。

公开(公告)号：US20090161434A1

公开(公告)日：2009-06-25

申请号：US11961917

申请日：2007-12-20

申请人： Feng Pan ,  Trung Pham ,  Byungki Woo

发明人： Feng Pan ,  Trung Pham ,  Byungki Woo

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/08 ,  G11C16/30

摘要： A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.

摘要翻译： 非易失性存储器件具有要并行感测的存储器单元的单独页面。 存储器件包括源极电平跟踪电路，其被耦合以从字线电压源接收预定字线电压，并在一个或多个页面的聚合源节点处接收电压电平，并被耦合以向存储器的字线提供输出电压 在感测操作期间，源电平跟踪电路包括运算放大器，由此输出电压是字线电压偏移量，以跟踪聚集节点处的电压电平，并补偿源极偏移误差，这是由于在 接地回路。

公开(公告)号：US08054681B2

公开(公告)日：2011-11-08

申请号：US12715858

申请日：2010-03-02

申请人： Feng Pan ,  Trung Pham ,  Byungki Woo

发明人： Feng Pan ,  Trung Pham ,  Byungki Woo

IPC分类号： G11C11/34

CPC分类号： G11C16/08 ,  G11C16/30

摘要： A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.

摘要翻译： 非易失性存储器件具有要并行感测的存储器单元的单独页面。 存储器件包括源极电平跟踪电路，其被耦合以从字线电压源接收预定字线电压，并在一个或多个页面的聚合源节点处接收电压电平，并被耦合以向存储器的字线提供输出电压 在感测操作期间，源电平跟踪电路包括运算放大器，由此输出电压是字线电压偏移量，以跟踪聚集节点处的电压电平，并补偿源极偏移误差，由于在 接地回路。

公开(公告)号：US07701761B2

公开(公告)日：2010-04-20

申请号：US11961917

申请日：2007-12-20

申请人： Feng Pan ,  Trung Pham ,  Byungki Woo

发明人： Feng Pan ,  Trung Pham ,  Byungki Woo

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C16/30

摘要： A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.

摘要翻译： 非易失性存储器件具有要并行感测的存储器单元的单独页面。 存储器件包括源极电平跟踪电路，其被耦合以从字线电压源接收预定字线电压，并在一个或多个页面的聚合源节点处接收电压电平，并被耦合以向存储器的字线提供输出电压 在感测操作期间，源电平跟踪电路包括运算放大器，由此输出电压是字线电压偏移量，以跟踪聚集节点处的电压电平，并补偿源极偏移误差，这是由于在 接地回路。

公开(公告)号：US20080158972A1

公开(公告)日：2008-07-03

申请号：US11617514

申请日：2006-12-28

申请人： Feng Pan ,  Trung Pham

发明人： Feng Pan ,  Trung Pham

IPC分类号： G11C16/26 ,  G11C7/12

CPC分类号： G11C7/12 ,  G11C16/24

摘要： Controlling a bitline bias voltage by sensing the bitline bias voltage, modifying a bitline bias control signal in accordance with the sensed bitline bias voltage, and controlling the bitline bias voltage in accordance with the modified bitline bias control signal. The modifying the bitline bias control signal is carried out by enabling a pull up circuit and disabling a pull down circuit in response to a first control signal and disabling the pull up circuit and enabling the pull down circuit in response to a second control signal.

摘要翻译： 通过感测位线偏置电压来控制位线偏置电压，根据感测到的位线偏置电压修改位线偏置控制信号，并根据修改的位线偏置控制信号控制位线偏置电压。 通过启用上拉电路和响应于第一控制信号禁用下拉电路并且禁用上拉电路并且响应于第二控制信号启用下拉电路来执行修改位线偏置控制信号。

公开(公告)号：US08106701B1

公开(公告)日：2012-01-31

申请号：US12895457

申请日：2010-09-30

申请人： Jonathan Hoang Huynh ,  Feng Pan ,  Qui Vi Nguyen ,  Trung Pham

发明人： Jonathan Hoang Huynh ,  Feng Pan ,  Qui Vi Nguyen ,  Trung Pham

IPC分类号： H03L5/00

CPC分类号： G11C16/08 ,  G11C16/30 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shifter circuit suitable for high voltage applications with shoot-through current isolation is presented. The level shifter receives a first enable signal and receives an input voltage at a first node and supplies an output voltage at a second node. The circuit provides the output voltage from the input voltage in response to the first enable signal being asserted and sets the output node to a low voltage value when the first enable signal is de-asserted. The level shifting circuit includes a depletion type NMOS transistor, having a gate connected to the output node, and a PMOS transistor, having a gate connected to the first enable signal. It also includes a first resistive element that is distinct from the NMOS and PMOS transistors. The NMOS transistor, the PMOS transistor and the first resistive elements are connected in series between the first and second nodes, with the NMOS transistor being connected to the first node. The level shifter further includes a discharge circuit connected to the second node and to receive a second enable signal. The second enable signal is asserted when the first enable signal is de-asserted and is asserted when the first enable signal is de-asserted, and the discharge circuit connects the second node to the low voltage value when the second enable signal is asserted and isolates the second node from ground when the second enable signal is de-asserted.

摘要翻译： 提出了适用于直流电流隔离的高电压应用的电平移位电路。 电平移位器接收第一使能信号并在第一节点处接收输入电压，并在第二节点处提供输出电压。 响应于第一使能信号被断言，电路提供来自输入电压的输出电压，并且当第一使能信号被解除置位时，将输出节点设置为低电压值。 电平移位电路包括具有连接到输出节点的栅极的耗尽型NMOS晶体管和具有连接到第一使能信号的栅极的PMOS晶体管。 它还包括与NMOS和PMOS晶体管不同的第一电阻元件。 NMOS晶体管，PMOS晶体管和第一电阻元件串联连接在第一和第二节点之间，NMOS晶体管连接到第一节点。 电平移位器还包括连接到第二节点并且接收第二使能信号的放电电路。 当第一使能信号被解除置位时，第二使能信号被置位，并且当第一使能信号被断言时被断言，并且当第二使能信号被断言时，放电电路将第二节点连接到低电压值 当第二使能信号被取消断言时，来自接地的第二节点。