ROUTING STRUCTURE AND METHOD OF WAFER SUBSTRATE WITH STANDARD INTEGRATION ZONE FOR INTEGRATION ON-WAFER

    公开(公告)号:US20240012977A1

    公开(公告)日:2024-01-11

    申请号:US18328800

    申请日:2023-06-05

    Applicant: ZHEJIANG LAB

    CPC classification number: G06F30/396 H01L27/0207 G06F2119/22

    Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

    SYSTEM-ON-WAFER STRUCTURE AND FABRICATION METHOD

    公开(公告)号:US20240006372A1

    公开(公告)日:2024-01-04

    申请号:US18328797

    申请日:2023-06-05

    Applicant: ZHEJIANG LAB

    Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.

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