公开(公告)号：US20170365571A1

公开(公告)日：2017-12-21

申请号：US15626916

申请日：2017-06-19

申请人： SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

发明人： Keita MATSUDA

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/13 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/11 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/1401 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/1412 ,  H01L2224/145

摘要： A semiconductor device having an electrode type of the ball grid array (BGA) and a process of forming the electrode are disclosed. The electrode insulating film, a seed layer on the insulating film, a mound metal on the insulating film and an interconnection on the seed layer. The mound metal surrounds the seed layer without forming any gap therebetween. The interconnection, which is formed by electroless plating, is apart from the insulating film with the mound metal as an extension barrier for the plating.

公开(公告)号：US20150371964A1

公开(公告)日：2015-12-24

申请号：US14840811

申请日：2015-08-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Cha ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Tsung-Hsien Chiang ,  Hao-Juin Liu ,  Yao-Chun Chuang ,  Chita Chuang

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L21/76897 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

摘要翻译： 所描述的实施例提供了在基本上面向封装结构的中心的铜柱的侧面上没有焊料润湿的封装结构的边缘附近的细长结合结构。 焊接润湿发生在这些结合结构的铜柱的另一侧。 细长结合结构被布置成不同的布置并且减小相邻结合结构之间短路的机会。 另外，细长的结合结构提高了可靠性。

公开(公告)号：US20150255369A1

公开(公告)日：2015-09-10

申请号：US14722745

申请日：2015-05-27

申请人： ROHM CO., LTD.

发明人： Shoji YASUNAGA ,  Mamoru YAMAGAMI

IPC分类号： H01L23/373 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49568 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0612 ,  H01L2224/06505 ,  H01L2224/14104 ,  H01L2224/145 ,  H01L2224/1451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4912 ,  H01L2224/495 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2924/01013 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： [Object]A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution]A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

摘要翻译： 半导体器件被配置为更有效地从半导体芯片释放热量。 解决方案的半导体器件包括：具有管芯焊盘主表面111和管芯焊盘后表面112的管芯焊盘11; 安装在芯片主表面111上的半导体芯片41; 密封树脂部分7，形成有用于暴露芯片垫背面11并覆盖芯片焊盘11和半导体芯片41的凹部75; 以及设置在凹部75中的散热层6.凹部75在芯片焊盘后表面112延伸的方向上具有凹部凹槽753，并且凹槽753更靠近模具垫主体 表面111相对于管芯焊盘后表面112.散热层6具有与管芯焊盘后表面112接触并且其部分填充凹槽753的接合层。

公开(公告)号：US20130001778A1

公开(公告)日：2013-01-03

申请号：US13610050

申请日：2012-09-11

申请人： Yuh Chern SHIEH ,  Han-Ping PU ,  Yu-Feng CHEN ,  Tin-Hao KUO

发明人： Yuh Chern SHIEH ,  Han-Ping PU ,  Yu-Feng CHEN ,  Tin-Hao KUO

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

摘要翻译： 描述了跟踪（BOT）结构。 BOT结构包括在第一工件的表面上具有金属迹线的第一工件，其中金属迹线具有第一轴线。 BOT结构还包括具有细长金属凸块的第二工件，其中细长金属凸块具有第二轴线，其中第二轴线与第一轴线成非零角度。 BOT结构还包括金属凸块，其中金属凸块电连接金属迹线和细长金属凸块。 还描述了具有BOT结构的封装和形成BOT结构的方法。

公开(公告)号：US20120273934A1

公开(公告)日：2012-11-01

申请号：US13095185

申请日：2011-04-27

申请人： Yuh Chern SHIEH ,  Han-Ping PU ,  Yu-Feng CHEN ,  Tin-Hao KUO

发明人： Yuh Chern SHIEH ,  Han-Ping PU ,  Yu-Feng CHEN ,  Tin-Hao KUO

IPC分类号： H01L23/498 ,  G06F17/50

CPC分类号： H01L24/14 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1405 ,  H01L2224/14131 ,  H01L2224/145 ,  H01L2224/16104 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2224/05552

摘要： The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.

摘要翻译： 凹凸跟踪（BOT）结构及其在芯片上的布局的实施例减少了金属焊盘上的电介质层和BOT结构的金属迹线上的应力。 通过将金属凸块的轴线定位成远离金属轨迹，可以减小应力，这可以降低金属迹线从基板和电介质层与金属垫分层的危险。 此外，金属焊盘和金属迹线上的电介质层的应力也可以通过将金属迹线的轴线朝向芯片的中心定向而减小。 结果，可以提高收率。

公开(公告)号：US09905499B2

公开(公告)日：2018-02-27

申请号：US15439625

申请日：2017-02-22

申请人： ROHM CO., LTD.

发明人： Shoji Yasunaga ,  Mamoru Yamagami

IPC分类号： H01L23/49 ,  H01L23/495 ,  H01L23/31 ,  H01L23/373

CPC分类号： H01L23/49568 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0612 ,  H01L2224/06505 ,  H01L2224/14104 ,  H01L2224/145 ,  H01L2224/1451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4912 ,  H01L2224/495 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2924/01013 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

公开(公告)号：US09613883B2

公开(公告)日：2017-04-04

申请号：US14722745

申请日：2015-05-27

申请人： ROHM CO., LTD.

发明人： Shoji Yasunaga ,  Mamoru Yamagami

IPC分类号： H01L23/00 ,  H01L23/373 ,  H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L21/56 ,  H01L23/367

CPC分类号： H01L23/49568 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0612 ,  H01L2224/06505 ,  H01L2224/14104 ,  H01L2224/145 ,  H01L2224/1451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4912 ,  H01L2224/495 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2924/01013 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/12042 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution]A semiconductor device includes: a die pad 11 which has a die pad main surface 111 and a die pad rear surface 112; a semiconductor chip 41 mounted on the die pad main surface 111; a sealing resin portion 7 formed with a recess 75 for exposure of the die pad rear surface 11 and covering the die pad 11 and the semiconductor chip 41; and a heat releasing layer 6 disposed in the recess 75. The recess 75 has a recess groove 753 outside the die pad 11 in a direction in which the die pad rear surface 112 extends, and the recess groove 753 is closer to the die pad main surface 111 than to the die pad rear surface 112. The heat releasing layer 6 has a junction layer which is in contact with the die pad rear surface 112 and having part thereof filling the recess groove 753.

公开(公告)号：US20170011979A1

公开(公告)日：2017-01-12

申请号：US14792650

申请日：2015-07-07

申请人： Diodes Incorporated

发明人： Duane Thomas Wilcoxen

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/762 ,  H01L23/00

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/76224 ,  H01L24/00 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/1182 ,  H01L2224/145

摘要： A novel semiconductor chip scale package encapsulates semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.

摘要翻译： 一种新型的半导体芯片级封装将半导体芯片封装在器件侧，非器件侧和四个边缘上，并具有模具化合物。 制造这种半导体芯片级封装的一个工艺包括在芯片周围的晶片表面上形成沟槽，并用第一模具化合物填充沟槽并覆盖芯片的器件侧。 随后，晶片从非器件侧变薄，直到沟槽的底部和该部分中的模具化合物也被去除。 稀化过程产生一个平面，其中包含芯片背面和模具化合物暴露在沟槽中。 该平面随后被第二模具化合物覆盖。

公开(公告)号：US08932933B2

公开(公告)日：2015-01-13

申请号：US13464645

申请日：2012-05-04

申请人： Ian C. Laboriante ,  Prashant Raghu

发明人： Ian C. Laboriante ,  Prashant Raghu

IPC分类号： H01L21/8242 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L24/11 ,  B81C1/00928 ,  H01L21/02063 ,  H01L21/321 ,  H01L24/14 ,  H01L28/90 ,  H01L2224/10155 ,  H01L2224/11019 ,  H01L2224/1182 ,  H01L2224/145 ,  H01L2924/01022 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2924/01104 ,  H01L2924/35

摘要： A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.

摘要翻译： 在半导体器件结构上形成疏水性表面的方法。 该方法包括形成至少一个具有至少一个包含钛原子的暴露表面的结构。 将至少一种结构的至少一个暴露表面与有机膦酸和有机磷酸中的至少一种接触以形成在至少一个结构的至少一个暴露表面上具有疏水表面的材料。 还描述了形成半导体器件结构和半导体器件结构的方法。

公开(公告)号：US08829673B2

公开(公告)日：2014-09-09

申请号：US13667306

申请日：2012-11-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Cha ,  Chita Chuang ,  Yao-Chun Chuang ,  Hao-Juin Liu ,  Tsung-Hsien Chiang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L21/76897 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

摘要翻译： 所描述的实施例提供了在基本上面向封装结构的中心的铜柱的侧面上没有焊料润湿的封装结构的边缘附近的细长结合结构。 焊接润湿发生在这些结合结构的铜柱的另一侧。 细长结合结构被布置成不同的布置并且减小相邻结合结构之间短路的机会。 另外，细长的结合结构提高了可靠性。