公开(公告)号：US11983481B2

公开(公告)日：2024-05-14

申请号：US18351464

申请日：2023-07-12

Applicant: ZHEJIANG LAB

Inventor： Zhiquan Wan ,  Shunbin Li ,  Ruyun Zhang ,  Weihao Wang ,  Qingwen Deng

IPC: G06F30/398 ,  G06F30/392 ,  G06F117/12

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2117/12

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

公开(公告)号：US11705437B1

公开(公告)日：2023-07-18

申请号：US18098726

申请日：2023-01-19

Applicant: ZHEJIANG LAB

Inventor： Qingwen Deng ,  Kun Zhang ,  Shunbin Li ,  Ruyun Zhang

IPC: H01L25/065 ,  H01L21/67 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/67103 ,  H01L23/481

Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.

公开(公告)号：US12112991B1

公开(公告)日：2024-10-08

申请号：US18497947

申请日：2023-10-30

Applicant: ZHEJIANG LAB

Inventor： Qingwen Deng ,  Kun Zhang ,  Ruyun Zhang

IPC: H01L23/00 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L22/22 ,  H01L22/32

Abstract: A system on wafer assembly structure and an assembly method thereof. The system on wafer assembly structure comprises: a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, and each provided with a bonding region, a testing region and an alignment region, respectively, a first assembly, and a second assembly, wherein the first assembly is arranged on one side of the wafer layer far away from the dielectric layer, and comprises a bearing portion and at least one latch portion connected with each other, and the bearing portion is detachably connected with the wafer layer. The second assembly is at least partially arranged around the first assembly. The second assembly has a hole portion for accommodating a latch portion, and the inner diameter of the hole portion is larger than the outer diameter of the latch portion.