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    Reducing CPU and bus power when running in power-save modes
    9.
    发明授权
    Reducing CPU and bus power when running in power-save modes 有权
    在省电模式下运行时，降低CPU和总线电源

    公开(公告)号：US07975161B2

    公开(公告)日：2011-07-05

    申请号：US11906473

    申请日：2007-10-02

    申请人： Opher Kahn

    发明人： Opher Kahn

    IPC分类号： G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G06F1/12

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  Y02D10/124 ,  Y02D10/126

    摘要： A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.

    摘要翻译： 处理系统包括总线和处理器，其核心被限制为具有不低于一个或多个总线时钟信号频率中最低的预定倍数的一个或多个核心时钟信号频率。 在省电模式下，处理器能够以频率生成一个或多个核心时钟信号，使得最低核心时钟信号频率低于性能模式中的一个或多个总线时钟信号频率中最低的预定倍数 。 处理器能够通过产生一个或多个总线时钟信号来实现这一点，使得省电模式中的最低总线时钟信号频率低于性能模式下总线时钟信号频率的最低值。