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    Method and Apparatus to Trace and Correlate Data Trace and Instruction Trace for Out-of-Order Processors
    3.
    发明申请
    Method and Apparatus to Trace and Correlate Data Trace and Instruction Trace for Out-of-Order Processors 有权
    跟踪和关联无序处理器的数据跟踪和指令跟踪的方法和设备

    公开(公告)号：US20090249302A1

    公开(公告)日：2009-10-01

    申请号：US12058874

    申请日：2008-03-31

    申请人： Zheng Xu ,  Suraj Bhaskaran ,  Klas M. Bruce ,  Jason T. Nearing ,  Paul B. Rawlins ,  Matt B. Smittle ,  Michael D. Snyder

    发明人： Zheng Xu ,  Suraj Bhaskaran ,  Klas M. Bruce ,  Jason T. Nearing ,  Paul B. Rawlins ,  Matt B. Smittle ,  Michael D. Snyder

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3636

    摘要： In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.

    摘要翻译： 在数据处理系统中，使用标记位来标识整个流水线中的数据访问指令，以指示该指令满足用户指定的标准（例如，满足感兴趣的数据地址范围）。 基于标记位，产生一个顺序程序相关消息，指示何时相对于指令流发生数据访问指令。 标记位还用于生成按顺序数据跟踪消息。 因此，仅包括满足用户指定标准的数据访问指令的跟踪流可以被后处理并且精确地相关联。

    System and method for serial interrupt scanning
    5.
    发明授权
    System and method for serial interrupt scanning 有权
    串行中断扫描的系统和方法

    公开(公告)号：US06263395B1

    公开(公告)日：2001-07-17

    申请号：US09227510

    申请日：1999-01-06

    申请人： Patrick L. Ferguson ,  Paul B. Rawlins ,  David F. Heinrich ,  Robert L. Woods

    发明人： Patrick L. Ferguson ,  Paul B. Rawlins ,  David F. Heinrich ,  Robert L. Woods

    IPC分类号： C06F1314

    CPC分类号： G06F13/24

    摘要： An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.

    摘要翻译： 中断控制器可以串行地扫描多个中断请求信号和/或在并行输入上接收中断请求信号。 扫描延迟可能与更新串行扫描中断请求的状态相关联。 寄生中断可能是由扫描延迟引起的。 为了减少伪中断的可能性，串行扫描的中断请求可能会在中断结束（EOI）之后被屏蔽一段时间。 清除中断请求的写周期可能会发布在写缓冲区中。 清除写缓冲区的这种写周期的延迟也可能导致虚假中断。 为了减少这种虚假中断的机会，EOI周期可能被延迟或重试，直到写入缓冲器清空。

    System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system
    6.
    发明授权
    System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system 有权
    计算机系统中系统接口设备与总线接口设备之间的点对点串行通信的系统和方法

    公开(公告)号：US06363439B1

    公开(公告)日：2002-03-26

    申请号：US09206515

    申请日：1998-12-07

    申请人： John D. Battles ,  Paul B. Rawlins ,  Robert Allan Lester ,  Patrick L. Ferguson

    发明人： John D. Battles ,  Paul B. Rawlins ,  Robert Allan Lester ,  Patrick L. Ferguson

    IPC分类号： G06F1314

    CPC分类号： G06F13/4273 ,  G06F13/4004

    摘要： A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the

    摘要翻译： 提供系统接口单元和外围总线接口单元之间的点对点串行通信链路。 系统总线接口单元可以在CPU总线和诸如PCI总线的外围总线之间进行接口，并且可以被称为北桥。 系统接口单元也可以连接到主存储器和高级图形端口。 外围总线接口单元可以在诸如PCI总线的第一外围总线和诸如ISA总线的第二外围总线之间进行接口，并且可以被称为南桥。 系统接口单元和总线接口单元之间的串行通信链路可以是使用来自第一外设总线的总线时钟作为定时参考的单线串行总线。 该时钟可能是PCI时钟。 串行通信链路可以使用系统接口单元上的单个引脚和总线接口单元上的单个引脚在接口单元之间传输命令。 可以在串行通信链路上提供上拉设备，以便当其不被总线接口单元中的一个驱动时，在链路上保持高电压电平。 北桥和南桥可以在发送和接收命令之间交替

    Next snoop predictor in a host controller
    7.
    发明授权
    Next snoop predictor in a host controller 有权
    主控制器中的下一个窥探预测器

    公开(公告)号：US06829665B2

    公开(公告)日：2004-12-07

    申请号：US09965871

    申请日：2001-09-28

    申请人： Phillip M. Jones ,  Paul B. Rawlins ,  Kenneth T. Chin

    发明人： Phillip M. Jones ,  Paul B. Rawlins ,  Kenneth T. Chin

    IPC分类号： G06F1300

    CPC分类号： G06F12/0831

    摘要： A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.

    摘要翻译： 一种用于优化周期时间以维持高速缓存一致性的技术。 具体地，提供了一种方法和装置，以优化在实现基于窥探的一致性方案的多处理器总线系统中的请求的处理。 为了最小化请求周期时间，同时执行窥探第一地址的总线和搜索发送队列以进行被窥探的下一个地址的动作。

    Method for improving processor performance
    9.
    发明授权
    Method for improving processor performance 失效
    提高处理器性能的方法

    公开(公告)号：US06961800B2

    公开(公告)日：2005-11-01

    申请号：US09967155

    申请日：2001-09-28

    申请人： Robert A. Lester ,  Kenneth T. Chin ,  Jim Blocker ,  John E. Larson ,  Phillip M. Jones ,  Paul B. Rawlins

    发明人： Robert A. Lester ,  Kenneth T. Chin ,  Jim Blocker ,  John E. Larson ,  Phillip M. Jones ,  Paul B. Rawlins

    IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/36

    CPC分类号： G06F13/1657

    摘要： Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

    摘要翻译： 提高处理器性能的方法。 具体地，通过减少主机控制器内的一些延迟周期，可以提高请求处理速度。 用于提高处理速度的一种技术涉及在从存储器控制器获得数据之前发起延迟回复事务。 第二种技术涉及预期从块下一个请求（BNR）状态转换到总线优先级请求（BPRI）状态的需要，从而消除了等待请求检查以确定是否必须实现BPRI状态的需要。