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    Method for fabrication of rear chip for hall effect magnetic head
    2.
    发明授权
    Method for fabrication of rear chip for hall effect magnetic head 失效
    霍尔效应磁头后置芯片的制造方法

    公开(公告)号：US4186481A

    公开(公告)日：1980-02-05

    申请号：US939210

    申请日：1978-09-05

    申请人： Takaharu Noguchi ,  Takao Ketori ,  Kohji Tamura ,  Tetsu Oi ,  Yutaka Miyoshi

    发明人： Takaharu Noguchi ,  Takao Ketori ,  Kohji Tamura ,  Tetsu Oi ,  Yutaka Miyoshi

    IPC分类号： G11B5/133 ,  G11B5/37 ,  G11B5/42

    CPC分类号： G11B5/376 ,  G11B5/1335 ,  Y10T29/49048 ,  Y10T29/49055

    摘要： A method for fabricating a rear core for the magnetic circuit of a Hall effect magnetic head is disclosed. The bottom size of the rear core protrusion is made substantially equal to the size of a Hall element. A gap is provided between the Hall element and the rear core. In order to minimize the gap, the rear core block is provided with supports for fabrication, whereby the gap between the Hall element and the bottom protrusion of the rear core is positioned accurately. The supports are removed at the end of fabrication. The bottom protrusion of the rear core prevented pressure from being applied to the Hall element, thus improving the sensitivity of the Hall effect magnetic head without increasing noises.

    摘要翻译： 公开了一种用于制造用于霍尔效应磁头的磁路的后芯的方法。 后芯突起的底部尺寸基本上等于霍尔元件的尺寸。 在霍尔元件和后芯之间提供间隙。 为了最小化间隙，后芯块设置有用于制造的支撑件，由此霍尔元件和后芯的底部突出部之间的间隙被精确地定位。 在制造结束时移除支撑件。 后芯的底部突起阻止了压力施加到霍尔元件，从而提高了霍尔效应磁头的灵敏度，而没有增加噪声。

    Address management system, interface ID setting processor, communication terminal, address management method, and computer program
    4.
    发明授权
    Address management system, interface ID setting processor, communication terminal, address management method, and computer program 失效
    地址管理系统，接口ID设置处理器，通信终端，地址管理方法和计算机程序

    公开(公告)号：US07272656B2

    公开(公告)日：2007-09-18

    申请号：US10214001

    申请日：2002-08-07

    申请人： Yutaka Miyoshi

    发明人： Yutaka Miyoshi

    IPC分类号： G06F15/17 ,  H04L12/28

    CPC分类号： H04L29/12254 ,  H04L29/12801 ,  H04L29/12839 ,  H04L61/2038 ,  H04L61/6004 ,  H04L61/6022 ,  H04L63/08 ,  H04L69/16 ,  H04L69/167 ,  H04W8/26

    摘要： In an address management system, an interface ID can be handed over from one apparatus to another without losing the correspondence between the interface ID and a user. As a result, the interface ID can be used as a unique identifier for the user. Accordingly, an effective infrastructure for individualized services is achieved. The interface ID may be constant for one user even when an apparatus is replaced, and thus IPv6 communication can be used as a user-associated address in high availability services, such as telephone services. Furthermore, the interface ID can be returned and reused, and thus the interface ID can be efficiently used.

    摘要翻译： 在地址管理系统中，可以将接口ID从一个装置切换到另一个装置，而不会丢失接口ID与用户之间的对应关系。 因此，接口ID可以用作用户的唯一标识符。 因此，实现了个性化服务的有效基础设施。 即使更换设备，接口ID也可以是一个用户的常数，因此IPv6通信可以用作诸如电话服务的高可用性服务中的用户相关地址。 此外，可以返回和重用接口ID，从而可以有效地使用接口ID。

    Frame data exchanging method and apparatus
    5.
    发明授权
    Frame data exchanging method and apparatus 失效
    帧数据交换方法和装置

    公开(公告)号：US06636507B1

    公开(公告)日：2003-10-21

    申请号：US09520274

    申请日：2000-03-07

    申请人： Yutaka Miyoshi ,  Junichi Hasegawa ,  Yoshiyuki Kunito

    发明人： Yutaka Miyoshi ,  Junichi Hasegawa ,  Yoshiyuki Kunito

    IPC分类号： H04L1256

    CPC分类号： H04L12/5601 ,  H04L47/10 ,  H04L47/30 ,  H04L2012/5647 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A frame switching apparatus in which it is possible to suppress the operating frequency of the bus and to suppress the cell loss ratio in comparison with that of an ATM cell switching apparatus employing the conventional input buffer system. Since the small capacity buffer Bn-n furnishes a transient storage site for a cell C, a distribution circuit 3n is able to receive a new cell Cn from the input buffer 2n to process the received cell. Therefore, head-of-line blocking is less likely to take place. On the other hand, since the small capacity buffer transfers the cell to only one output port, it is sufficient if the switching matrix SWM is of a N:1 multiplexer structure which is far simpler than a complete cross-bandwidth available register structure.

    摘要翻译： 与采用常规输入缓冲系统的ATM信元交换装置相比，可以抑制总线的工作频率并抑制信元丢失率的帧切换装置。 由于小容量缓冲器Bn-n为单元C提供瞬时存储位置，所以分配电路3n能够从输入缓冲器2n接收新单元Cn以处理接收的单元。 因此，线路阻塞不太可能发生。 另一方面，由于小容量缓冲器将单元传送到仅一个输出端口，所以如果开关矩阵SWM是具有比完整的跨带宽可用寄存器结构简单得多的N：1多路复用器结构就足够了。