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25 条记录 (耗时 0.056 秒)

    Method for managing and controlling the low power modes for an integrated circuit device
    4.
    发明授权
    Method for managing and controlling the low power modes for an integrated circuit device 有权
    用于管理和控制集成电路器件的低功率模式的方法

    公开(公告)号：US08909956B2

    公开(公告)日：2014-12-09

    申请号：US12813265

    申请日：2010-06-10

    申请人： Zhiqing Zhuang ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani ,  Soheyla Kamal

    发明人： Zhiqing Zhuang ,  Jalil Fadavi-Ardekani ,  Vinay Kumar Bhasin ,  Lawrence John Madar, III ,  Chenmin Zhang ,  Vafa James Rakshani

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3296 ,  Y02D10/128 ,  Y02D10/172

    摘要： A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

    摘要翻译： 包括其相关输入输出（IO）在内的状态机和外部接口总是通电并用于管理芯片功率模式和功率模式转换。 芯片功率模式被定义为RUN，HIBERNATE，POWERDOWN，本发明可能更多。 例如，一旦设备处于HIBERNATE或POWERDOWN模式，除了该控制器状态机之外，IC的电源被减少或完全断开。 本发明的状态机和控制机制响应于一些外部“唤醒事件”，通过其控制接口管理外部电源的状态，将芯片带到RUN模式。 该实现实现了小芯片尺寸和极低的功耗。

    Parameter memory for hardware accelerator
    5.
    发明授权
    Parameter memory for hardware accelerator 失效
    硬件加速器的参数存储器

    公开(公告)号：US06842844B1

    公开(公告)日：2005-01-11

    申请号：US09512511

    申请日：2000-02-24

    申请人： Jalil Fadavi-Ardekani ,  Walter G. Soto ,  Wayne Xin

    发明人： Jalil Fadavi-Ardekani ,  Walter G. Soto ,  Wayne Xin

    IPC分类号： G06F13/40 ,  G06F15/17 ,  G06F15/177 ,  H04M11/06

    CPC分类号： H04M11/062

    摘要： The present invention provides a hardware accelerator of a DSP with a parameter RAM memory for storing the parameters required for the various operating conditions of the accelerator. The hardware accelerator can easily and without modification accommodate design changes such as the need to support additional ADSL lines.

    摘要翻译： 本发明提供了具有参数RAM存储器的DSP的硬件加速器，用于存储加速器的各种操作条件所需的参数。 硬件加速器可以轻松而无需修改，可以满足设计更改，例如需要支持额外的ADSL线路。

    Interrupt mechanism using TDM serial interface
    6.
    发明授权
    Interrupt mechanism using TDM serial interface 失效
    中断机制采用TDM串行接口

    公开(公告)号：US06263075B1

    公开(公告)日：2001-07-17

    申请号：US08927425

    申请日：1997-09-11

    申请人： Jalil Fadavi-Ardekani ,  Donald Raymond Laturell

    发明人： Jalil Fadavi-Ardekani ,  Donald Raymond Laturell

    IPC分类号： H04M300

    CPC分类号： H04M3/005

    摘要： An improvement to split-architecture audio codecs such as those defined by the Audio Codec '97 specification (AC '97) includes an interrupt mechanism which allows an event at an analog peripheral device such as an incoming call to be sensed by the AC analog sub-system and initiate a wake up procedure in the split-architecture audio codec system. The interrupt mechanism includes a masked interrupt register which is responsive to an interrupt signal from an audio source, such as a ring detect from an incoming telephone line. Either the AC controller sub-system or the peripheral analog device via the AC analog sub-system can initiate a wake up procedure. The AC controller sub-system includes a static divide by 256 counter responsive to a bit clock signal. The bit clock signal is sensed at the AC controller sub-system to determine an operating mode. Upon detection of at least 256 bit clock cycles after a predetermined minimum time for the AC analog sub-system to be in a halted or sleep mode, a wake up interrupt register is enabled in the AC controller sub-system. The interrupt sensor is opto-coupled to the AC analog sub-system, and the interrupt signal from the interrupt sensor is communicated to the AC controller sub-system via the five-wire TDM serial bus between the AC analog sub-system and the AC controller sub-system.

    摘要翻译： 对诸如由Audio Codec'97规范（AC '97）定义的解码架构音频编解码器的改进包括允许在诸如来电的模拟外围设备的事件由AC模拟子系统感测的中断机制 系统，并在分裂架构音频编解码器系统中启动唤醒过程。 中断机制包括屏蔽中断寄存器，其响应来自音频源的中断信号，例如来自输入电话线路的环检测。 AC控制器子系统或通过AC模拟子系统的外围模拟设备可以启动唤醒过程。 AC控制器子系统响应于位时钟信号包括256位计数器的静态除法。 在AC控制器子系统处感测位时钟信号以确定操作模式。 在AC模拟子系统处于停止或睡眠模式的预定最小时间之后检测至少256位时钟周期，在AC控制器子系统中启用唤醒中断寄存器。 中断传感器与AC模拟子系统光耦合，中断传感器的中断信号通过AC模拟子系统与AC之间的5线TDM串行总线传送给交流控制器子系统 控制器子系统。

    On-demand transfer engine
    7.
    发明授权
    On-demand transfer engine 有权
    按需传输引擎

    公开(公告)号：US06230215B1

    公开(公告)日：2001-05-08

    申请号：US09188904

    申请日：1998-11-10

    申请人： Jalil Fadavi-Ardekani ,  Srinivasa Gutta ,  Walter G. Soto ,  Avinash Velingker ,  Daniel K. Greenwood

    发明人： Jalil Fadavi-Ardekani ,  Srinivasa Gutta ,  Walter G. Soto ,  Avinash Velingker ,  Daniel K. Greenwood

    IPC分类号： G06F300

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F11/349 ,  G06F12/0646 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0278 ,  Y02D10/128 ,  Y02D10/34

    摘要： An on-demand transfer (ODT) engine is located in each peripheral in a host/peripheral system communicating using a burst mode bus, e.g., a PCI bus. Each peripheral transfers blocks by setting, e.g., a starting address and block size of a data block to be transferred. Importantly, the starting location of a data transfer stream is maintained in a common memory area, e.g., in the host, while the length of the data transfer block is maintained in the ODT engine. By maintaining the length of the data block in the ODT engine, the peripheral can change the length of a block in a continual data stream on the fly, without the need to communicate with the host computer or common data transfer device such as a DMA. In the disclosed embodiment, up to 128 data streams may be simultaneously transferred.

    摘要翻译： 按需传输（ODT）引擎位于使用突发模式总线（例如PCI总线）通信的主机/外围设备系统的每个外围设备中。 每个外设通过设置例如要传送的数据块的起始地址和块大小来传送块。 重要的是，数据传输流的起始位置保持在公共存储器区域中，例如在主机中，而数据传输块的长度保持在ODT引擎中。 通过保持ODT引擎中数据块的长度，外设可以随时更改连续数据流中块的长度，而无需与主机或公共数据传输设备（如DMA）通信。 在所公开的实施例中，多达128个数据流可以被同时传送。

    Dynamic partitioning of memory banks among multiple agents
    8.
    发明授权
    Dynamic partitioning of memory banks among multiple agents 失效
    内存库在多个代理之间进行动态分区

    公开(公告)号：US06965974B1

    公开(公告)日：2005-11-15

    申请号：US09120126

    申请日：1998-07-22

    申请人： Laurence Edward Bays ,  Jalil Fadavi-Ardekani ,  Srinivasa Gutta ,  Bahram Ghaffarzadeh Kermani ,  Richard Joseph Niescier ,  Geoffrey Lawrence Smith ,  Walter G. Soto ,  Daniel K. Greenwood

    发明人： Laurence Edward Bays ,  Jalil Fadavi-Ardekani ,  Srinivasa Gutta ,  Bahram Ghaffarzadeh Kermani ,  Richard Joseph Niescier ,  Geoffrey Lawrence Smith ,  Walter G. Soto ,  Daniel K. Greenwood

    IPC分类号： G06F12/00 ,  G06F12/06

    CPC分类号： G06F12/0607

    摘要： A multiple agent system providing each of a plurality of agents, e.g., processors, to access a shared synchronous or asynchronous memory. In the case of synchronous memory, the clock signal from a super agent selected from among the plurality of agents provides a memory access clock signal to the other agents accessing the same shared memory. The other agents synchronize their respective address, data and control busses to those of the super agent, and output a representation of the same clock signal to the shared memory. In another aspect of the present invention, the shared memory is partitioned for use from among a plurality of groups of agents, each agent group comprising one or more agents. Any one of the agents may update a configuration register to flexibly reconfigure the amount of shared memory available to the agents as necessary.

    摘要翻译： 提供多个代理（例如处理器）中的每一个以访问共享同步或异步存储器的多代理系统。 在同步存储器的情况下，从多个代理中选择的来自超级代理的时钟信号向访问同一共享存储器的其他代理提供存储器访问时钟信号。 其他代理将其各自的地址，数据和控制总线同步到超级代理的总线，并将相同时钟信号的表示输出到共享存储器。 在本发明的另一方面，共享存储器被划分为在多组代理之间使用，每个代理组包括一个或多个代理。 任何一个代理可以更新配置寄存器，以便根据需要灵活地重新配置代理可用的共享内存量。

    Processor powerdown operation using intermittent bursts of instruction clock
    9.
    发明授权
    Processor powerdown operation using intermittent bursts of instruction clock 有权
    处理器断电操作使用间歇性突发的指令时钟

    公开(公告)号：US06275948B1

    公开(公告)日：2001-08-14

    申请号：US09141511

    申请日：1998-08-27

    申请人： Laurence E. Bays ,  Jalil Fadavi-Ardekani ,  Kenneth Daniel Fitch ,  Richard Joseph Niescier

    发明人： Laurence E. Bays ,  Jalil Fadavi-Ardekani ,  Kenneth Daniel Fitch ,  Richard Joseph Niescier

    IPC分类号： G06F126

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F11/349 ,  G06F12/0646 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0278 ,  Y02D10/128 ,  Y02D10/34

    摘要： An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.

    摘要翻译： 根据本发明的原理，处于低功率模式的处理单元的指令时钟由突发模式控制信号限定。 突发模式控制信号被允许启动和停止相关处理单元的指令流。 在所公开的实施例中，主时钟信号被时钟控制电路限定，以向相关处理单元提供指令时钟信号的脉冲串。 为了操作突发指令周期控制单元，用户将突发长度预编程到寄存器中，以将指令周期的长度设置到相关处理单元。 计数器中的最大计数器值设置提供给相关处理单元的指令周期突发的周期。 只要计数器的当前值小于或等于预编程突发长度，突发控制信号允许时钟控制器将主时钟信号或其他相关时钟信号作为指令时钟信号传递到相关处理 单元。 低功率突发模式，因此功率节省可以根据突发长度和最大计数器值的组合值进行调整。

    Signal processing system having reduced memory space
    10.
    发明授权
    Signal processing system having reduced memory space 失效
    信号处理系统具有减少的存储空间

    公开(公告)号：US5412740A

    公开(公告)日：1995-05-02

    申请号：US231346

    申请日：1994-04-21

    申请人： Jalil Fadavi-Ardekani

    发明人： Jalil Fadavi-Ardekani

    IPC分类号： H04N1/387 ,  G06F17/16 ,  G06T1/60 ,  H04N7/015 ,  H04N7/30 ,  G06K9/00

    CPC分类号： G06T1/60

    摘要： A signal processing system includes means for performing a logic function on a multi-dimensional array of information stored in a memory. Typically, the memory stores two-dimensional video information (pixels), and the logic function is a discrete cosine transform (DCT), or other linear operation. The logic function is performed on both rows and columns of the information. In the prior art, this has required two memory spaces, so that information could be written into one memory while being read out of another memory. In the present invention, a single memory space is used to transpose the information between row and column format, by performing a read-modify-write operation on each memory location in a specified sequence.

    摘要翻译： 信号处理系统包括用于对存储在存储器中的信息的多维阵列执行逻辑功能的装置。 通常，存储器存储二维视频信息（像素），并且逻辑功能是离散余弦变换（DCT）或其他线性操作。 对信息的行和列执行逻辑功能。 在现有技术中，这需要两个存储器空间，使得可以在从另一个存储器读出的同时将信息写入一个存储器。 在本发明中，通过以指定的顺序对每个存储器位置执行读 - 修改 - 写操作，使用单个存储器空间来转移行和列格式之间的信息。