公开(公告)号：US20090253238A1

公开(公告)日：2009-10-08

申请号：US12099726

申请日：2008-04-08

申请人： Zhonghai SHI ,  David WU ,  Jingrong ZHOU ,  Ruigang LI

发明人： Zhonghai SHI ,  David WU ,  Jingrong ZHOU ,  Ruigang LI

IPC分类号： H01L21/8234

CPC分类号： H01L21/823437 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

摘要翻译： 提供了一种用于FinFET器件的制造工艺。 该过程开始于提供具有诸如硅的导电材料层的半导体晶片。 然后由导电材料层形成翅片的全场排列。 翅片的全场布置包括具有均匀间距和均匀翅片厚度的多个导电翅片。 接下来，在翅片的整个场布置上形成切割掩模。 切割掩模选择性地屏蔽翅片的全场布置的部分，其布局限定了用于多个FinFET器件的特征。 切割掩模用于去除翅片的全场排列的一部分，该部分未被切割掩模保护。 所得到的翅片结构用于完成FinFET器件的制造。

公开(公告)号：US20090081837A1

公开(公告)日：2009-03-26

申请号：US11861492

申请日：2007-09-26

申请人： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

发明人： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/78 ,  H01L29/7843

摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

摘要翻译： 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US20100285650A1

公开(公告)日：2010-11-11

申请号：US12463221

申请日：2009-05-08

申请人： Zhonghai SHI ,  Jingrong ZHOU

发明人： Zhonghai SHI ,  Jingrong ZHOU

IPC分类号： H01L21/265 ,  H01L21/266

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

摘要翻译： 制造半导体器件的方法开始于提供或制造包括半导体材料和形成在半导体材料上的多个栅极结构的器件结构。 通过用相对于半导体材料的暴露表面的非倾斜角的离子轰击器件结构，通过在半导体材料中产生光剂量延伸植入物来继续该方法。 在该步骤期间，多个栅极结构被用作第一注入掩模。 该方法通过形成覆盖半导体材料的图案化掩模来继续，图案化掩模布置成保护半导体材料的共享漏极区域并且使半导体材料的共享源极区域基本上暴露。 此后，该方法通过用离子以相对于半导体材料的暴露表面倾斜的角度并且朝向多个栅极结构轰击器件结构而在半导体材料中产生大剂量延伸植入物和/或晕轮植入物。 在该步骤期间，多个栅极结构和图案化掩模用作第二注入掩模。

公开(公告)号：US20100214008A1

公开(公告)日：2010-08-26

申请号：US12392645

申请日：2009-02-25

申请人： Ruigang LI ,  David Donggang WU ,  James F. BULLER ,  Jingrong ZHOU

发明人： Ruigang LI ,  David Donggang WU ,  James F. BULLER ,  Jingrong ZHOU

IPC分类号： H01H37/76 ,  H01L29/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01H9/50 ,  H01H35/24 ,  H01H77/101 ,  H01L27/11206

摘要： A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.

摘要翻译： 提供了一种编程基于晶体管的熔丝结构的方法。 熔丝结构在具有半导体衬底的半导体器件，形成在半导体衬底上的晶体管器件和形成在半导体衬底上的基于晶体管的熔丝结构的半导体器件中实现。 基于晶体管的熔丝结构包括多个基于晶体管的熔丝，并且该方法开始于从多个基于晶体管的熔丝中选择待编程的第一目标熔丝，以在低电阻/高电流状态下工作 所述第一靶保险丝在所述第一栅极和所述半导体衬底之间具有第一源极，第一栅极，第一漏极和第一栅极绝缘体层。 该方法将第一组编程电压施加到第一源极，第一栅极和第一漏极，以引起第一栅极绝缘体层的击穿，使得电流可以通过第一栅极绝缘体层从第一源极流到第一栅极 ，并且通过第一栅极绝缘体层从第一栅极到第一漏极。

公开(公告)号：US20090081860A1

公开(公告)日：2009-03-26

申请号：US11861534

申请日：2007-09-26

申请人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

发明人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

摘要翻译： 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。