公开(公告)号：US08134208B2

公开(公告)日：2012-03-13

申请号：US11861928

申请日：2007-09-26

申请人： Zhonghai Shi ,  David Wu ,  Mark Michael ,  Donna Michael, legal representative

发明人： Zhonghai Shi ,  David Wu ,  Mark Michael

IPC分类号： H01L27/12

CPC分类号： H01L29/41733 ,  H01L21/28518 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

摘要翻译： 提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。 这些半导体器件包括半导体器件结构和接触。 在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

公开(公告)号：US08003466B2

公开(公告)日：2011-08-23

申请号：US12099726

申请日：2008-04-08

申请人： Zhonghai Shi ,  David Wu ,  Jingrong Zhou ,  Ruigang Li

发明人： Zhonghai Shi ,  David Wu ,  Jingrong Zhou ,  Ruigang Li

IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763 ,  H01L27/148 ,  H01L29/66 ,  H01L29/76 ,  H01L21/12 ,  H01L27/088

CPC分类号： H01L21/823437 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

摘要翻译： 提供了一种用于FinFET器件的制造工艺。 该过程开始于提供具有诸如硅的导电材料层的半导体晶片。 然后由导电材料层形成翅片的全场排列。 翅片的全场布置包括具有均匀间距和均匀翅片厚度的多个导电翅片。 接下来，在翅片的整个场布置上形成切割掩模。 切割掩模选择性地屏蔽翅片的全场布置的部分，其布局限定了用于多个FinFET器件的特征。 切割掩模用于去除翅片的全场排列的一部分，该部分未被切割掩模保护。 所得到的翅片结构用于完成FinFET器件的制造。

公开(公告)号：US20070257322A1

公开(公告)日：2007-11-08

申请号：US11382149

申请日：2006-05-08

申请人： Zhonghai Shi ,  Voon-Yew Thean ,  Ted White

发明人： Zhonghai Shi ,  Voon-Yew Thean ,  Ted White

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L21/8238

CPC分类号： H01L27/0688 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/78696

摘要： A topography (40) is provided which includes a device having a transistor formed from a stack of semiconductor layers (42/46). The different semiconductor layers are spaced apart by a gate (60) and by support structures (48) comprising a material having different etch characteristics than the materials of the spaced apart semiconductor layers. The device includes a first transistor channel (76) within the upper semiconductor layer and, in some cases, further includes a second transistor channel within the lower semiconductor layer. The resulting hybrid transistor structure may be fabricated as one of a pair of CMOS transistors, the other of which may include the same configuration or a different configuration. A method for fabricating the hybrid transistor structure includes forming a gate structure surrounding a suspended portion (52) of an upper patterned semiconductor layer (53) and extending down to a surface of a lower semiconductor layer (42).

摘要翻译： 提供了一种形状（40），其包括具有由半导体层堆叠（42/46）形成的晶体管的器件。 不同的半导体层由栅极（60）和支撑结构（48）间隔开，支撑结构（48）包括具有与间隔开的半导体层的材料不同的蚀刻特性的材料。 该器件包括在上半导体层内的第一晶体管沟道（76），并且在一些情况下还包括下半导体层内的第二晶体管沟道。 所得到的混合晶体管结构可以制造为一对CMOS晶体管之一，另一个可以包括相同的配置或不同的配置。 一种用于制造混合晶体管结构的方法包括：形成围绕上图案化半导体层（53）的悬垂部分（52）并向下延伸到下半导体层（42）的表面的栅极结构。

公开(公告)号：US20070085624A1

公开(公告)日：2007-04-19

申请号：US11251467

申请日：2005-10-14

申请人： Hector Sanchez ,  Zhonghai Shi

发明人： Hector Sanchez ,  Zhonghai Shi

IPC分类号： H03L7/099

CPC分类号： H03L7/0995 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00065 ,  H03L7/089

摘要： A VCO has a plurality of MIGFETs coupled to provide phase adjustment in response to receiving digital phase adjustment control signals. The VCO includes a ring oscillator implemented as a plurality of serially coupled inverters. A phase adjustment circuit is coupled to the output of each inverter. The phase adjustment circuit of each stage comprises a predetermined number of MIGFETs. In one embodiment, half of the MIGFETs are used to speed-up the phase/frequency of the OUTPUT signal a predetermined amount in response to receiving speed-up control signals. The other half of the MIGFETs are used to slow-down the phase/frequency of the OUTPUT signal a predetermined amount in response to the receiving slow-down control signals. The VCO requires relatively less surface area, is simple, and is easy to implement.

公开(公告)号：US08026142B2

公开(公告)日：2011-09-27

申请号：US12463221

申请日：2009-05-08

申请人： Zhonghai Shi ,  Jingrong Zhou

发明人： Zhonghai Shi ,  Jingrong Zhou

IPC分类号： H01L21/00

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

摘要翻译： 制造半导体器件的方法开始于提供或制造包括半导体材料和形成在半导体材料上的多个栅极结构的器件结构。 通过用相对于半导体材料的暴露表面的非倾斜角的离子轰击器件结构，通过在半导体材料中产生光剂量延伸植入物来继续该方法。 在该步骤期间，多个栅极结构被用作第一注入掩模。 该方法通过形成覆盖半导体材料的图案化掩模来继续，图案化掩模布置成保护半导体材料的共享漏极区域并且使半导体材料的共享源极区域基本上暴露。 此后，该方法通过用离子以相对于半导体材料的暴露表面倾斜的角度并且朝向多个栅极结构轰击器件结构而在半导体材料中产生大剂量延伸植入物和/或晕轮植入物。 在该步骤期间，多个栅极结构和图案化掩模用作第二注入掩模。

公开(公告)号：US07838345B2

公开(公告)日：2010-11-23

申请号：US11416436

申请日：2006-05-02

申请人： Zhonghai Shi ,  Bich-Yen Nguyen ,  Héctor Sánchez

发明人： Zhonghai Shi ,  Bich-Yen Nguyen ,  Héctor Sánchez

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

摘要翻译： 电子设备可以包括与另一个间隔开的第一半导体鳍片和第二半导体鳍片。 电子设备还可以分别包括位于第一半导体鳍片和第二半导体鳍片之间并且分别仅与第一半导体鳍片和第二半导体鳍片的每一个的长度的一部分接触的桥接器。 在另一方面，一种用于形成电子器件的方法可以包括从半导体层形成第一半导体鳍片和第二半导体鳍片，每个第一半导体鳍片和第二半导体鳍片彼此间隔开。 该工艺还可以包括形成接触第一半导体鳍片和第二半导体鳍片的桥。 该方法还可以包括形成位于第一半导体鳍片和第二半导体鳍片之间的包括栅电极的导电构件。

公开(公告)号：US20100285650A1

公开(公告)日：2010-11-11

申请号：US12463221

申请日：2009-05-08

申请人： Zhonghai SHI ,  Jingrong ZHOU

发明人： Zhonghai SHI ,  Jingrong ZHOU

IPC分类号： H01L21/265 ,  H01L21/266

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

摘要翻译： 制造半导体器件的方法开始于提供或制造包括半导体材料和形成在半导体材料上的多个栅极结构的器件结构。 通过用相对于半导体材料的暴露表面的非倾斜角的离子轰击器件结构，通过在半导体材料中产生光剂量延伸植入物来继续该方法。 在该步骤期间，多个栅极结构被用作第一注入掩模。 该方法通过形成覆盖半导体材料的图案化掩模来继续，图案化掩模布置成保护半导体材料的共享漏极区域并且使半导体材料的共享源极区域基本上暴露。 此后，该方法通过用离子以相对于半导体材料的暴露表面倾斜的角度并且朝向多个栅极结构轰击器件结构而在半导体材料中产生大剂量延伸植入物和/或晕轮植入物。 在该步骤期间，多个栅极结构和图案化掩模用作第二注入掩模。

公开(公告)号：US07761838B2

公开(公告)日：2010-07-20

申请号：US11861492

申请日：2007-09-26

申请人： Zhonghai Shi ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

发明人： Zhonghai Shi ,  Mark Michael ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

IPC分类号： G06F17/50 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/78 ,  H01L29/7843

摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

摘要翻译： 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US20080023803A1

公开(公告)日：2008-01-31

申请号：US11496106

申请日：2006-07-31

申请人： Zhonghai Shi ,  Voon-Yew Thean ,  Ted R. White

发明人： Zhonghai Shi ,  Voon-Yew Thean ,  Ted R. White

IPC分类号： H01L29/04 ,  H01L21/84

CPC分类号： H01L29/66795 ,  H01L29/045 ,  H01L29/785

摘要： A method is provided for making a semiconductor device, comprising (a) providing a semiconductor stack comprising a first semiconductor layer (407) having a crystallographic orientation and a second semiconductor layer (405) having a crystallographic orientation; (b) defining an oxide mask (415) in the first semiconductor layer; and (c) utilizing the oxide mask to pattern the second semiconductor layer.

摘要翻译： 提供一种用于制造半导体器件的方法，包括（a）提供包括具有<110>晶体取向的第一半导体层（407）和具有<100>晶体取向的第二半导体层（405）的半导体堆叠; （b）在第一半导体层中限定氧化物掩模（415）; 和（c）利用该氧化物掩模对第二半导体层进行图案化。

公开(公告)号：US20080020515A1

公开(公告)日：2008-01-24

申请号：US11458902

申请日：2006-07-20

申请人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

发明人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

IPC分类号： H01L21/00

CPC分类号： H01L21/845 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

摘要翻译： 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。