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    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER
    1.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER 有权
    用于制造具有延伸应力衬里的半导体器件的方法

    公开(公告)号：US20090081837A1

    公开(公告)日：2009-03-26

    申请号：US11861492

    申请日：2007-09-26

    申请人： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

    发明人： Zhonghai SHI ,  Mark MICHAEL ,  David WU ,  James F. BULLER ,  Jingrong ZHOU ,  Akif SULTAN ,  Donna Michael

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/78 ,  H01L29/7843

    摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

    摘要翻译： 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

    ELECTRONIC DEVICE AND METHOD OF BIASING
    2.
    发明申请
    ELECTRONIC DEVICE AND METHOD OF BIASING 有权
    电子设备和偏置方法

    公开(公告)号：US20090090969A1

    公开(公告)日：2009-04-09

    申请号：US11867743

    申请日：2007-10-05

    申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

    发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

    摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

    METHOD OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES USING HALO IMPLANT SHADOWING
    3.
    发明申请
    METHOD OF FORMING TRANSISTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES USING HALO IMPLANT SHADOWING 有权
    使用HALO IMPLANT SHADOWING形成具有不同阈值电压的晶体管器件的方法

    公开(公告)号：US20090081860A1

    公开(公告)日：2009-03-26

    申请号：US11861534

    申请日：2007-09-26

    申请人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

    发明人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

    摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

    摘要翻译： 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

    STRESS ENHANCED SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME
    4.
    发明申请
    STRESS ENHANCED SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME 有权
    应力增强半导体器件及其制造方法

    公开(公告)号：US20090078991A1

    公开(公告)日：2009-03-26

    申请号：US11861051

    申请日：2007-09-25

    申请人： Akif SULTAN ,  Mark MICHAEL ,  David WU ,  Donna Michael

    发明人： Akif SULTAN ,  Mark MICHAEL ,  David WU ,  Donna Michael

    IPC分类号： H01L29/78 ,  H01L21/762

    CPC分类号： H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

    摘要： A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

    摘要翻译： 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。