公开(公告)号：US20210366764A1

公开(公告)日：2021-11-25

申请号：US16647304

申请日：2018-08-23

Applicant: ams AG

Inventor： Georg Parteder ,  Jochen Kraft ,  Raffaele Coppeta

IPC: H01L21/768 ,  H01L23/48

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.

公开(公告)号：US11367672B2

公开(公告)日：2022-06-21

申请号：US17052452

申请日：2019-03-20

Applicant: ams AG

Inventor： Jochen Kraft ,  Georg Parteder ,  Anderson Pires Singulani ,  Raffaele Coppeta ,  Franz Schrank

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent of the contact layer is smaller than the lateral extent of the via or the lateral extent of the contact layer amounts to at least 2.5 times the lateral extent of the via.

公开(公告)号：US20210005534A1

公开(公告)日：2021-01-07

申请号：US16968815

申请日：2019-02-15

Applicant: ams AG

Inventor： Victor Sidorov ,  Stefan Jessenig ,  Georg Parteder

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768

Abstract: A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate.

公开(公告)号：US11764109B2

公开(公告)日：2023-09-19

申请号：US16980197

申请日：2019-04-03

Applicant: ams AG

Inventor： Jochen Kraft ,  Georg Parteder ,  Stefan Jessenig ,  Franz Schrank ,  Jörg Siegert

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481

Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.

公开(公告)号：US11355386B2

公开(公告)日：2022-06-07

申请号：US16647304

申请日：2018-08-23

Applicant: ams AG

Inventor： Georg Parteder ,  Jochen Kraft ,  Raffaele Coppeta

IPC: H01L21/768 ,  H01L23/48

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.

公开(公告)号：US12211769B2

公开(公告)日：2025-01-28

申请号：US17639736

申请日：2020-08-27

Applicant: ams AG

Inventor： Georg Parteder ,  Jochen Kraft ,  Stefan Jessenig

IPC: H01L23/48 ,  H01L21/768

Abstract: An open through-substrate via, TSV, comprises an insulation layer disposed adjacent to at least a portion of side walls of a trench and to a surface of a substrate body. The TSV further comprises a metallization layer disposed adjacent to at least a portion of the insulation layer and to at least a portion of a bottom wall of said trench, a redistribution layer disposed adjacent to at least a portion of the metallization layer and a portion of the insulation layer disposed adjacent to the surface, and a capping layer disposed adjacent to at least a portion of the metallization layer and to at least a portion of the redistribution layer. The insulation layer and/or the capping layer comprise sublayers that are distinct from each other in terms of material properties. A first of the sublayers is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface and a second of the sublayers is disposed adjacent to at least a portion of the surface.

公开(公告)号：US11127656B2

公开(公告)日：2021-09-21

申请号：US16483884

申请日：2018-02-14

Applicant: ams AG

Inventor： Jochen Kraft ,  Georg Parteder ,  Anderson Singulani ,  Raffaele Coppeta ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.

公开(公告)号：US20210020511A1

公开(公告)日：2021-01-21

申请号：US16980197

申请日：2019-04-03

Applicant: ams AG

Inventor： Jochen Kraft ,  Georg Parteder ,  Stefan Jessenig ,  Franz Schrank ,  Jörg Siegert

IPC: H01L21/768 ,  H01L23/48

Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.

公开(公告)号：US20200020611A1

公开(公告)日：2020-01-16

申请号：US16483884

申请日：2018-02-14

Applicant: ams AG

Inventor： Jochen Kraft ,  Georg Parteder ,  Anderson Singulani ,  Raffaele Coppeta ,  FRANZ SCHRANK

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.