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    Semiconductor device with through-substrate via
    1.
    发明授权
    Semiconductor device with through-substrate via 有权

    公开(公告)号：US11367672B2

    公开(公告)日：2022-06-21

    申请号：US17052452

    申请日：2019-03-20

    Applicant: ams AG

    Inventor： Jochen Kraft ,  Georg Parteder ,  Anderson Pires Singulani ,  Raffaele Coppeta ,  Franz Schrank

    IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

    Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent of the contact layer is smaller than the lateral extent of the via or the lateral extent of the contact layer amounts to at least 2.5 times the lateral extent of the via.

    Method of producing an optical sensor at wafer-level and optical sensor
    2.
    发明授权
    Method of producing an optical sensor at wafer-level and optical sensor 有权

    公开(公告)号：US10734534B2

    公开(公告)日：2020-08-04

    申请号：US15746342

    申请日：2016-07-22

    Applicant: ams AG

    Inventor： Harald Etschmaier ,  Gregor Toschkoff ,  Thomas Bodner ,  Franz Schrank

    IPC: H01L31/0203 ,  H01L31/0232 ,  H01L31/173 ,  G01J1/02 ,  G01J5/04 ,  H01L23/00 ,  H01L31/02 ,  H01L31/153

    Abstract: A method of producing an optical sensor at wafer-level, comprising the steps of providing a wafer having a main top surface and a main back surface and arrange at or near the top surface of the wafer at least one first integrated circuit having at least one light sensitive component. Furthermore, providing in the wafer at least one through-substrate via for electrically contacting the top surface and back surface and forming a first mold structure by wafer-level molding a first mold material over the top surface of the wafer, such that the first mold structure at least partly encloses the first integrated circuit. Finally, forming a second mold structure by wafer-level molding a second mold material over the first mold structure, such that the second mold structure at least partly encloses the first mold structure.

    Method of producing an interposer-chip-arrangement for dense packaging of chips
    4.
    发明授权
    Method of producing an interposer-chip-arrangement for dense packaging of chips 有权

    公开(公告)号：US10340254B2

    公开(公告)日：2019-07-02

    申请号：US15726905

    申请日：2017-10-06

    Applicant: ams AG

    Inventor： Jochen Kraft ,  Martin Schrems ,  Franz Schrank

    IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538

    Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.

    Method for manufacturing a semiconductor device and semiconductor device
    7.
    发明授权
    Method for manufacturing a semiconductor device and semiconductor device 有权

    公开(公告)号：US11139207B2

    公开(公告)日：2021-10-05

    申请号：US16754323

    申请日：2018-10-11

    Applicant: ams AG

    Inventor： Thomas Bodner ,  Stefan Jessenig ,  Franz Schrank

    IPC: H01L21/768 ,  H01L21/56 ,  H01L23/48

    Abstract: A method for manufacturing a semiconductor device comprises the steps of providing a semiconductor body with a main plane of extension, and forming a trench in the semiconductor body from a top side of the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body. The method further comprises the steps of coating inner walls of the trench with an isolation layer, depositing a metallization layer within the trench, and depositing a passivation layer within the trench such that an inner volume of the trench is free of any material, wherein inner surfaces that are adjacent to the inner volume are treated to be hydrophobic at least in places. Furthermore, a semiconductor device is provided.

    SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION
    9.
    发明申请
    SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION AND METHOD OF PRODUCING A SEMICONDUCTOR DEVICE FOR DETECTION OF RADIATION 审中-公开
    用于检测辐射的半导体器件和用于产生用于检测辐射的半导体器件的方法

    公开(公告)号：US20160020238A1

    公开(公告)日：2016-01-21

    申请号：US14772055

    申请日：2014-02-24

    Applicant: ams AG

    Inventor： Hubert Enichlmair ,  Franz Schrank ,  Joerg Siegert

    IPC: H01L27/146

    CPC classification number: H01L27/14621 ,  H01L23/481 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13024

    Abstract: The semiconductor device for detection of radiation comprises a semiconductor substrate (1) with a main surface (11), a dielectric layer (6) comprising at least one compound of a semiconductor material, an integrated circuit (2) including at least one component sensitive to radiation (3), a wiring (4) of the integrated circuit embedded in an intermetal layer (8) of the dielectric layer (6), an electrically conductive through-substrate via (5) contacting the wiring, and an optical filter element (7) arranged immediately on the dielectric layer above the component sensitive to radiation. The dielectric layer comprises a passivation layer (9) at least above the through-substrate via, the passivation layer comprises a dielectric material that is different from the intermetal layer (8), and the wiring is arranged between the main surface and the passivation layer.

    Abstract translation: 用于检测辐射的半导体器件包括具有主表面（11）的半导体衬底（1），包括至少一种半导体材料的化合物的电介质层（6），包括至少一个组件敏感的集成电路（2） 辐射（3），嵌入电介质层（6）的金属间层（8）中的集成电路的布线（4），与布线接触的导电贯穿基板通孔（5）和光学滤波器元件 （7）立即布置在对辐射敏感的部件上方的电介质层上。 介电层包括至少在贯通基板通孔上方的钝化层（9），钝化层包括不同于金属间层（8）的介电材料，并且布线布置在主表面和钝化层之间 。

    Crack-resistant semiconductor devices
    10.
    发明授权
    Crack-resistant semiconductor devices 有权

    公开(公告)号：US11127656B2

    公开(公告)日：2021-09-21

    申请号：US16483884

    申请日：2018-02-14

    Applicant: ams AG

    Inventor： Jochen Kraft ,  Georg Parteder ,  Anderson Singulani ,  Raffaele Coppeta ,  Franz Schrank

    IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L23/00

    Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.

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