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    BONDED STRUCTURE AND METHOD FOR MANUFACTURING A BONDED STRUCTURE
    1.
    发明申请
    BONDED STRUCTURE AND METHOD FOR MANUFACTURING A BONDED STRUCTURE 有权

    公开(公告)号：US20220317391A1

    公开(公告)日：2022-10-06

    申请号：US17640185

    申请日：2020-08-25

    Applicant: ams AG

    Inventor： Jochen Kraft ,  Bernhard Stering ,  Colin Steele ,  Jean Francois Seurin

    IPC: G02B6/42

    Abstract: A bonded structure comprises a substrate component having a plurality of first pads arranged on or within a surface of the substrate component, and an integrated circuit component having a plurality of second pads arranged on or within a surface of the integrated circuit component. The bonded structure further comprises a plurality of connection elements physically connecting the first pads to the second pads. The surface of the integrated circuit component is tilted obliquely to the surface of the substrate component at a tilt angle that results from nominal variations of surface sizes of the first and second pads.

    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210366764A1

    公开(公告)日：2021-11-25

    申请号：US16647304

    申请日：2018-08-23

    Applicant: ams AG

    Inventor： Georg Parteder ,  Jochen Kraft ,  Raffaele Coppeta

    IPC: H01L21/768 ,  H01L23/48

    Abstract: A method for manufacturing a semiconductor device is provided. The method comprises the steps of providing a semiconductor body, forming a trench in the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body, and coating inner walls of the trench with an isolation layer. The method further comprises the steps of coating the isolation layer at the inner walls with a metallization layer, coating a top side of the semiconductor body, at which the trench is formed, at least partially with an electrically conductive contact layer, where the contact layer is electrically connected with the metallization layer, coating the top side of the semiconductor body at least partially and the trench with a capping layer, and forming a contact pad at the top side of the semiconductor body by removing the contact layer and the capping layer at least partially. Furthermore, a semiconductor device is provided.

    Semiconductor device with through-substrate via
    6.
    发明授权
    Semiconductor device with through-substrate via 有权

    公开(公告)号：US11367672B2

    公开(公告)日：2022-06-21

    申请号：US17052452

    申请日：2019-03-20

    Applicant: ams AG

    Inventor： Jochen Kraft ,  Georg Parteder ,  Anderson Pires Singulani ,  Raffaele Coppeta ,  Franz Schrank

    IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

    Abstract: A semiconductor device includes a semiconductor body, an electrically conductive via which extends through at least a part of the semiconductor body, and where the via has a top side and a bottom side that faces away from the top side, an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to a lateral direction, where the lateral direction is perpendicular to a vertical direction given by the main axis of extension of the via, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the lateral direction. The etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction, the lateral extent in the lateral direction of the etch-stop layer amounts to at least 2.5 times the lateral extent of the via in the lateral direction, and the lateral extent of the contact layer is smaller than the lateral extent of the via or the lateral extent of the contact layer amounts to at least 2.5 times the lateral extent of the via.

    Method of producing an interposer-chip-arrangement for dense packaging of chips
    8.
    发明授权
    Method of producing an interposer-chip-arrangement for dense packaging of chips 有权

    公开(公告)号：US10340254B2

    公开(公告)日：2019-07-02

    申请号：US15726905

    申请日：2017-10-06

    Applicant: ams AG

    Inventor： Jochen Kraft ,  Martin Schrems ,  Franz Schrank

    IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538

    Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.

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